Lam Research Corporation

Applied Materials, Inc.

Noel Sun

Nicolas Gani

Yoshie Kimura

Radhika C Mani

Alex Paterson

Meihua Shen

Gowri Kamarthy

Monica Titus

Do Young Kim

Helene Del Puppo

Jen-Kan Yu

Ting-Ying Chung

Ellie Y Yieh

Thorsten B Lill

Stefan Schmitz

Weimin Zeng

Uday Mitra

Ganesh Upadhyaya

Xiang Zhou

Michael Goss

Chung Liu

Naveed Ansari

Phil Friddle

Jae Ho Lee

Changwoo Lee

Weiye Zhu

Han-Hsiang Chen

Zhaohong Han

Eric Pei

Seokhwan Lee

Methods and apparatuses for passivating a fin field effect transistor (FinFET) semiconductor device and performing a gate etch using integrated atomic layer deposition (ALD) and etch processes are described herein. Methods include performing a partial gate etch, depositing a passivation layer on exposed surfaces of semiconductor fins and a gate layer by ALD, and performing a final gate etch to form one or more gate structures of the FinFET semiconductor device. The etch, deposition, and etch processes are performed in the same plasma chamber. The passivation layer is deposited on sidewalls of the gate layer to maintain a gate profile of the one or more gate structures during etching.

Atomic layer deposition and etch in a single plasma chamber for fin field effect transistor formation

A method of performing a sidewall image transfer (SIT) process includes arranging a substrate within a substrate processing chamber, wherein the substrate includes a mandrel layer formed on the substrate and etching the mandrel layer to form a plurality of mandrels. The method further includes, without removing the substrate from within the substrate processing chamber and subsequent to etching the mandrel layer, depositing a thin spacer layer such that the thin spacer layer is formed on upper surfaces of the plurality of mandrels, sidewalls of the plurality of mandrels, and portions of the substrate between the sidewalls of the plurality of mandrels, subsequent to depositing the thin spacer layer, etching the thin spacer layer to remove the thin spacer layer from the upper surfaces of the mandrels and the portions of the substrate between the sidewalls of the plurality of mandrels such that only the thin spacer layer formed on the sidewalls of the plurality of mandrels remains, and, subsequent to etching the thin spacer layer from the upper surfaces of the mandrels and the portions of the substrate between the sidewalls of the plurality of mandrels, etching the plurality of mandrels to remove the plurality of mandrels from the substrate such that only the thin spacer layer formed on the sidewalls of the plurality of mandrels remains on the substrate.

Systems and methods for performing in-situ deposition of sidewall image transfer spacers

The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber. The ion-ion plasma may be used to advantage in a variety of etching processes.

Internal plasma grid applications for semiconductor fabrication

Embodiments of the invention include methods for in-situ chamber dry cleaning a plasma processing chamber utilized for gate structure fabrication process in semiconductor devices. In one embodiment, a method for in-situ chamber dry clean includes supplying a first cleaning gas including at least a boron containing gas into a processing chamber in absence of a substrate disposed therein, supplying a second cleaning gas including at least a halogen containing gas into the processing chamber in absence of the substrate, and supplying a third cleaning gas including at least an oxygen containing gas into the processing chamber in absence of the substrate.

Methods for in-situ chamber clean utilized in an etching processing chamber

Internal plasma grid applications for semiconductor fabrication in context of ion-ion plasma processing

Methods for fabricating a semiconductor device having a lanthanum-family-based oxide layer are described. A gate stack having a lanthanum-family-based oxide layer is provided above a substrate. At least a portion of the lanthanum-family-based oxide layer is modified to form a lanthanum-family-based halide portion. The lanthanum-family-based halide portion is removed with a water vapor treatment.

Method for fabricating a semiconductor device having a lanthanum-family-based oxide layer

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Sunnyvale, CA, United States of America

Noel Sun