Xilinx, Inc.

Other

Noel J Brady

Peter H Alfke

Lars-Olof B Svensson

Lionel Edward Barker

Adrian W O'Reilly

A cache system includes a computational cache and a computational cache miss-handler. The computational cache is configured to cache state vectors and perform read-modify-write (RMW) operations on the cached state vectors responsive to received RMW commands. The computational cache miss-handler is configured to perform RMW operations on state vectors stored in a memory responsive to cache misses in the computational cache. The memory is external to the cache system.

Cached system for managing state vectors

A circuit measures a time interval between a first event and a second event. One or more activity inputs receive a respective signal indicating the first and second events. For each activity input, a respective high-speed serial receiver includes a sampling circuit and a deserializer. The sampling circuit generates sample bits from sampling the respective signal at active edges of a clock signal. The deserializer converts the sample bits into a sequence of parallel data words. The sample bits undergo a first change in response to the first event and a second change in response to the second event. An arithmetic circuit receives the sequence of parallel data words from the respective high-speed serial receiver. The arithmetic circuit determines a number of the sample bits between the first and second changes in the sequence of parallel data words. The number measures the time interval between the first and second events.

Circuit for measuring a time interval using a high-speed serial receiver

Data recovery, as well as associated circuitry and system, is described. An input word stream having a word width of at least one word is obtained and a sliding window is applied to it to resolve phases. Scores for phases are determined at least in part by: subdividing the sliding window into sample portions; applying a homogeneity function to each of the sample portions to determine respective values therefor; and summing sets of the values respectively associated with the phases to provide the scores. A score is selected from the scores according to at least one criterion to select a phase from the phases. A portion of a delayed version of the input word stream is sampled by application of the sliding window thereto using the phase selected to output sampled bits.

Digital data recovery

A bicycle braking system for permitting controlled rotation and continuous power to the wheels of a bicycle during braking of the bicycle to enhance control of the bicycle during braking includes a cylindrical brake pad that is spring loaded within angled slots in a casing. The brake pad is positioned proximate the rim of a wheel and a cable assembly is coupled to the brake pad for urging the brake pad towards an end of the angled slots and against the rim of the wheel to slow rotation of the wheel.

Growing community of inventors

Dublin, Ireland

Noel J Brady