Hewlett-packard Company

Hewlett-packard Development Company, L.p.

Noel D Scott

Alan S Krech, Jr

Eugene Dvoskin

Daniel M Olsen

Robert J Casey

Eric M Rentschler

Peter Andrew Seiler

Adolfo Adolfo Gomez

Don W Dyer

Robert J Horning

Kenneth William Shrum

John R Pessetto

A power monitoring adapter may include a plurality of power supply unit (PSU) inputs to couple a plurality of PSUs to the power monitoring adapter. The power monitoring adapter may also include a power output to electrically couple the power monitoring adapter to a powered system. The power output includes a voltage line, and a ground. Further, the power monitoring adapter may include a side band interface to couple to the powered system. The side band interface communicates status data of the number of PSUs coupled to the power monitoring adapter.

Power monitoring adapters

A clamping circuit includes an energy storage section and a pulse generator to generate a pulse in which the energy storage section stores energy from a main power supply.

Clamping circuit

Reporting electrical current to a processor. At least some of the illustrative embodiments are methods including providing operational power to a processor at a voltage indicated by the processor of a computer system, measuring electrical current actually drawn by the processor, and reporting to the processor a value of electrical current drawn by the processor. The value of electrical current reported different than the electrical current actually drawn by more than a measurement error of measuring the electrical current actually drawn.

Method and system of reporting electrical current to a processor

A high precision, memory efficient method for the compression of surface normals and the inverse method for the decompression of those compressed surface normals back into surface normals. The normals are first scaled to unit length in Cartesian coordinates. Then, each of the smallest two vector components of the unit length normal is stored along with an indicator of which of the three vector components is not stored plus the algebraic sign of that vector component. Decompression of the surface normal requires first converting the two stored vector components into floating-point values and then using the equation 1&equals;x &plus;y &plus;z in order to obtain the non-stored vector component of the unit length normal.

Surface normal compression/decompression storing two vector components

An occlusion culling circuit for use in a graphics computer receives graphics primitives data including x and y coordinates for each pixel, a z depth value, and r, g, b, and a or index color data. For each group of primitives, the graphics computer scans the primitive and determines a volume which completely bounds the primitive. The z depth values for the pixels comprising the bounding volume are then compared by the occlusion culling circuit to the depths of the pixels in the already rendered primitives to determine whether any pixels in the incoming primitive are visible. If no pixels are visible, the occlusion culling circuit clears the result register and receives the next graphics primitive. If, on the other hand, one or more pixels is visible, the occlusion culling circuit completely renders the primitives bounded by the bounding volume. Since the graphics primitives which are totally occluded can bypass the more intensive pixel by pixel processing and storage, the speed and efficiency of the graphics computer can be significantly increased.

System and method for accelerated occlusion culling

A graphics processor is disclosed having two processing units and two dual-port RAMs for passing data between the processing units. The hardware is configured to process two graphics primitives simultaneously in a first mode, and to use both processing units simultaneously to process a single primitive in a second mode. One of the dual-port RAMs may function as a FIFO buffer in the second mode. A method for processing graphics primitives is disclosed in which one processing unit generates a set of intermediate results for a first primitive and stores them in a first RAM, and then generates a set of intermediate results for a second primitive and stores them in a second RAM while another processing unit reads the first RAM and completes calculations for the first primitive. Afterwards, the second processing unit reads the second RAM and completes calculations for the second primitive. Another method for processing graphics primitives is disclosed in which the first processing unit generates two sets of intermediate results for the same primitive, and in which the second processing unit generates final results for the primitive in two parts.

Method and apparatus for processing graphics primitives in multiple

A system and associated method for dynamically allocating vertex data to a plurality of geometry accelerators in a computer graphics system based upon the relative current capability of the geometry accelerators to process the data. This efficient distribution of vertex data substantially reduces the amount of time individual geometry accelerators remain idle, thereby increasing both the efficiency of each geometry accelerator as well as the overall parallel processing of vertex data. This selective utilization of geometry accelerators thereby results in a significant increase in the throughput performance of the computer graphics system. A computer graphics system in accordance with the present invention comprises a plurality of geometry accelerators and a distributor connected through two unidirectional buses that transmit data in opposite directions. The geometry accelerators are connected, through appropriate interfacing hardware, directly to an input bus. The geometry accelerators are also coupled to an output bus in a manner that enables them to control the flow of data generated by upstream geometry accelerators. This dual bus arrangement enables the distributor to control the allocation of vertex data while enabling the geometry accelerators to control the subsequent combining of resulting rendering data.

System and method for dynamically allocating data among geometry

A clamping system is designed to clamp floating point values from a geometry accelerator in a computer graphics system. The clamping system includes a register configured to receive the floating point value from a connection from the geometry accelerator in the graphics system. Logic associated with the register is configured to determine when the value is less than or equal to a first threshold value (preferably, 0), greater than or equal to a second threshold value (preferably, 1), and between the first and second threshold values. An output mechanism is controlled by the logic. In the preferred embodiment, the output mechanism is a multiplexer interconnected with a tristate driver. The output mechanism is configured to output onto the connection the first threshold value when the color value is less than or equal to the first threshold value, to output onto the connection the second threshold value when the color value is greater than or equal to the second threshold value, and to output onto the connection the originally received floating point value when the floating point value is between the first and second threshold values. An absolute value logic mechanism is associated with the clamping system. The absolute value logic mechanism is configured to force a sign bit of the value that is output by the output mechanism to exhibit a positive state so that the absolute value of an incoming floating point value can be accomplished.

Clamping system and method for clamping floating point color values from

An enhanced performance queuing system that includes a FIFO queue in an electronic device, where the FIFO queue is controlled by a FIFO queue controller that also provides FIFO queue status relating to space available in the FIFO queue. A first device writes data to the FIFO queue in data chunks or in data item increments within a data chunk. FIFO queue status is requested only to determine if a data chunk sized space is free prior to writing to a data chunk space in the FIFO queue, rather than polling for FIFO queue status prior to each write operation. A second device reads data from the FIFO queue in data chunks or data item increments from within a data chunk. The first device begins writing to the FIFO queue prior to signaling the second device to begin reading, so that the second device can read from the FIFO queue without ever catching up with the first device thereby eliminating the need for requesting FIFO queue status to determine if data is available for reading.

Asynchronous FIFO queuing system operating with minimal queue status

Apparatus for determining an integer power of a floating point number includes a shift register, a register file having a partial product register and a binary power register, a multiplier coupled to the register file for performing floating point multiply operations and a state machine for controlling the shift register, the register file and the multiplier. The state machine controls loading of initial values into the shift register and into the partial product register and the binary power register. The state machine controls execution of an integer power routine in which a new partial product value is determined by multiplying the contents of the partial product register by the contents of the binary power register if the LSB of the shift register is a 1. The partial product value is left unchanged if the LSB of the shift register is a 0. A new binary power value is determined by multiplying the contents of the binary power register by itself. Then the contents of the shift register are shifted one bit to the right, and the integer power routine is repeated until all bits in the shift register are 0's.

Growing community of inventors

Fort Collins, CO, United States of America

Noel D Scott