International Business Machines Corporation

Noel Arellano

Rudy J Wojtecki

Ekmini Anuja De Silva

Kristin Schmidt

Daniel Sanders

Teddie Peregrino Magbitang

Ankit Vora

Son Van Nguyen

Zhenxing Bi

Hosadurga K Shobha

Chi-Chun Liu

Damon B Farmer

Muthumanickam Sankarapandian

Chun Wing Yeung

Cornelius Brown Peethala

Matthew Warren Copel

Gregory Michael Wallraff

Joy Cheng

Charles Thomas Rettner

Hoa D Truong

Robin Hsin Kuo Chao

Thomas J Haigh, Jr

Balasubramanian S Pranatharthi Haran

Alexander M Friz

Krystelle Lionti

Jed Walter Pitera

Aakash Pushp

Noah F Fine Nathel

Alexander Edward Hess

Anthony Fong

Brian Peter Hughes

Benjamin Madon

M A Mueed

Vincent Ouazan-Reboul

Forming a hardmask layer for reactive ion etching includes depositing a hardmask above an underlayer. The hardmask includes a layer of magnesium oxide having a thickness of up to 10 nm. A resist layer is deposited above the hardmask and developed to form a pattern that exposes portions of the hardmask. The pattern is transferred from the resist layer to the hardmask by rinsing exposed portions of the hardmask with a deionized water solution.

Magnesium oxide based hardmask for reactive ion etching

Embodiments are provided for fabrication of superconducting devices using area-selective deposition of a metal nitride. In some embodiments, a method can include providing a thermally treated carbon layer, and selectively depositing a metal nitride using the thermally treated carbon layer for formation of a superconducting device.

Area-selective deposition of metal nitride to fabricate devices

A patterning method is described that utilizes self-assembled monolayers (SAMs) formed with hydroxamic acid compounds and area selective atomic layer deposition (ALD). In the examples, regions of the SAM exposed to extreme ultraviolet radiation (EUV) become resistant to ALD deposition. Subsequent treatment of the exposed SAM to an ALD process results in selective growth of an ALD film on the non-exposed regions of the SAM, leaving the exposed regions substantially free of ALD material.

EUV patterning of monolayers for selective atomic layer deposition

A method is presented for forming a fully aligned via (FAV) structure. The method includes depositing a first dielectric adjacent a conductive material, forming a surface aligned monolayer (SAM) over the conductive material, the SAM defining a long chain SAM formed by a layer-by-layer growth technique, depositing a second dielectric over the SAM and the first dielectric, performing chemical mechanical polishing (CMP) to planarize the second dielectric, and etching the SAM to form the FAV structure.

Selective deposition with SAM for fully aligned via

A method for fabricating a semiconductor device includes forming a via in a first dielectric layer arranged on a metal layer. The via exposes a portion of the metal layer. The method includes forming a trench in the first dielectric layer. The method further includes depositing, by a selective process, a second dielectric layer on the first dielectric layer such that the second dielectric layer lines sidewalls of the via and the trench and is selectively deposited onto the first dielectric layer.

Selective deposition of dielectrics on ultra-low k dielectrics

A method for manufacturing a semiconductor device includes forming a first nanosheet device and forming a second nanosheet device spaced apart from the first nanosheet device in respective first and second regions corresponding to first and second types. The first and second nanosheet devices respectively include a first and a second plurality of work function metal layers, and a work function metal layer extends from the first and second plurality of work function metal layers in the space between the nanosheet devices. In the method, part of the work function metal layer is removed from the space between the nanosheet devices, and the removed part of the work function metal layer is replaced with a polymer brush layer. The first plurality of work function metal layers is selectively removed from the first region with respect to the polymer brush layer.

Undercut control in isotropic wet etch processes

A high-chi diblock copolymer (BCP) for self-assembly comprises a first block comprising repeat units of trimethylsilyl styrene (TMSS) and styrene, and a second block comprising an aliphatic carbonate repeat unit. The blocks are linked together by a fluorinated junction group L' in which none of the fluorines of L&#x2032; are covalently bound to an atomic center of the polymer backbone. A top-coat free film layer comprising the BCP, which is disposed on an underlayer and in contact with an atmosphere, is capable of forming a perpendicularly oriented lamellar domain pattern on an underlayer that is preferential or non-preferential to the domains of the block copolymer. The domain pattern can be selectively etched to provide a relief pattern comprising a remaining domain. The relief pattern having good critical dimensional uniformity compared to an otherwise identical polymer lacking the silicon.

Thin film self assembly of topcoat-free silicon-containing diblock copolymers

Block copolymers (BCPs) for self-assembly applications comprise a linear fluorinated linking group L' joining a pair of adjacent blocks. A film layer comprising a BCP, which is disposed on an underlayer and in contact with an atmosphere, is capable of forming a perpendicularly oriented domain pattern when the underlayer is preferentially wetted by one domain of an otherwise identical self-assembled BCP in which all fluorines of L&#x2032; are replaced by hydrogen. The BCP can be a low-chi or high-chi BCP. In a preferred embodiment, the BCP comprises a styrene-based first block, and a second block comprises a carbonate and/or ester repeat unit formed by ring opening polymerization of a cyclic carbonate and/or cyclic ester monomer. The linking group L&#x2032; has a lower surface energy than each of the polymer blocks.

Block copolymers for directed self-assembly applications

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Noel Arellano