Kabushiki Kaisha Toshiba

Tokyo Shibaura Denki Kabushiki Kaisha

Tokyo Shibaura Denki Kabushiki

Nobuyuki Toyoda

Akimichi Hojo

Toshiyuki Terada

Takamaro Mizoguchi

Yasuo Ikawa

Naotaka Uchitomi

Kiyoho Kamei

Katsue Kanazawa

Riro Nii

In an IC device, an IC body having a predetermined function and high-frequency circuits for testing high-frequency characteristics of the IC body are formed on a single chip. The test circuits include an L-H frequency conversion circuit arranged on the input side of the IC body and an H-L frequency conversion circuit arranged on the output side. The test circuits can switch a connecting state between the conversion circuits and the IC body in response to an external control signal. The test circuits can be disconnected from the IC body after a test is completed.

IC chip test circuit for high frequency integrated circuits

A GaAs JFET according to the present invention is formed as follows. First, an n type active layer is formed on a GaAs substrate. Then, a gate electrode containing a group II element is formed on the n type active layer. With the gate electrode being used as a mask, an n type impurity is ion-implanted in the GaAs substrate with a high concentration in a self-aligned fashion with respect to the gate electrode. Heat-treatment is then performed on the resultant structure to diffuse the group II element in the gate electrode into the n type active layer, forming a p type gate region. At the same time, the ion-implanted n type impurity is activated, forming source and drain regions.

Method of making a GaAs JFET with self-aligned p-type gate by

A semiconductor integrated circuit device according to the present invention comprising an electric circuit formed in a semiconductor substrate, said circuit including first and second nodes between which a potential difference is provided, a wiring of a large ground capacitance connected to the first node, and a bypass capacitor connected to the second node, said wiring and bypass capacitor being of an integral structure prepared by laminating an upper conductor film pattern connected to the second node via an insulating film on a lower conductor film pattern connected to the first node. A MIM-structure in which a wiring and a bypass capacitor are made integral is employed in the semiconductor integrated circuit device of the present invention, making it possible to eliminate the large area required for forming the independent bypass capacitor. Also, the ratio of the ground capacitance of the wiring to the capacitance of the bypass capacitor is constant regardless of the change in the length of the wiring.

Semiconductor integrated circuit device having an integrally formed

A gate array integrated circuit in which gate cells are each composed of a DCFL circuit using Schottky-barrier FETs. A plurality of basic gate cells is arrayed in one direction to form a basic cell array, and such basic cell arrays are arranged parallel to each other. VDD lines and GND lines are provided to apply an operating voltage to the basic gate cells. In order to stably operate the gate array integrated circuit of DCFL structure in which the logical amplitude and noise margin are small, the VDD lines and the GND lines are arranged perpendicular to each other such that the number of the basic gate cells which are connected to each of the VDD lines is larger than that of the basic gate cells which are connected to each of the GND lines. According to this layout, the potential difference (voltage drop) developed in the GND lines by operation current is reduced.

Gate array integrated circuit using Schottky-barrier FETs

An etched SiO.sub.2 film component serving as a mask at the time of formation of source and drain electrodes in a surface layer of a GaAs substrate by means of ion implantation is side-etched before a gate electrode is formed. An SiO.sub.2 film component has a narrowed width smaller than a distance between the source and drain electrodes while the SiO.sub.2 film component supports a metal mask patterned film at its top surface. The SiO.sub.2 film component is replaced with a metal layer serving as a gate of a self-aligned Schottky gate FET. According to this method, a metal with high heat resistance need not be used as a metal material of the gate layer.

Manufacturing method of Schottky gate FET

In an integrated logic circuit employing normally-off type FET's, it is difficult, but desirable to realize a NAND gate due to unwanted flow of the forward current to the next stage. In accordance with the invention, a stable NAND gate operation can be realized by introducing a NOR gate into all gate electrodes of the inputs of the NAND gate, except one gate electrode thereof of which source is grounded.

Ga/As NOR/NAND gate circuit using enhancement mode FET's

A process for manufacturing a buried gate field effect transistor having a small effective gate length, which process enables precise control of the threshold voltage. First, a compound semiconductor crystal having a first impurity region as a source region, a second impurity region as a drain region and a channel layer buried inside the compound semiconductor crystal is prepared by a conventional process. A V-shaped groove is then formed with an etching solution having high selectivity toward the crystal face in the gate region of this compound semiconductor crystal. Onto the inner wall surface of the V-shaped groove, a metal likely to form an alloy type of Schottky junction with the compound semiconductor is vapor-deposited. The resultant structure is heated, while measuring the threshold voltage, to form an alloy type of Schottky junction and for use of this junction as a gate electrode.

Process for manufacturing a buried gate field effect transistor

A Schottky gate FET is fabricated by forming on a semiconductor substrate first and second stacks facing each other. Each stack is constructed by an ohmic electrode and a spacer film. On the substrate having stacks formed thereon an insulation layer is formed and is anisotropically etched in the direction of its thickness until the planar surface portions are exposed. As a result, portions of the insulation layer remain on opposing side walls of the stacks. After removing the spacer films to define stepped portions between each remaining portion and each electrode, a layer of a metallic material capable of forming a Schottky barrier with the substrate is formed. The remaining portions are removed to pattern the metallic material layer, thereby forming a Shottky gate electrode.

Growing community of inventors

Yokohama, Japan

Nobuyuki Toyoda