Megachips Corporation

Ntt Electronics Corporation

Nobuyuki Takasu

Hiromu Hasegawa

Akira Okamoto

Makoto Saito

Naotsugu Yamamura

Takashi Matsumoto

Kazuhiro Saito

Norihiko Nagai

Takeaki Komuro

Mayumi Okumura

An encryption circuit includes a fundamental vector generation circuit configured to generate a random number sequence for serving as a fundamental vector based on an initial vector, an image mask generation circuit configured to generate an image mask with a mask value set for each pixel in a region to be encrypted smaller than a frame size of the image, based on the fundamental vector and coordinate information for specifying the region to be encrypted, and an XOR operation circuit configured to compute an exclusive OR between each mask value of the image mask and each pixel value of the image data to generate encrypted image data.

Encryption device, computer-readable recording medium, and encryption method

In an earliest vertical synchronization period after sending an encoded image data is restarted, a first reference image determination circuit determines to employ a local decoded image generated in a vertical synchronization period immediately preceding a vertical synchronization period in which an error occurs among multiple local decoded images stored in a first DRAM as a reference image. In an earliest vertical synchronization period after a decoding circuit is reset, a second reference image determination circuit determines to employ a decoded image generated in the vertical synchronization period immediately preceding the vertical synchronization period in which the error occurs among multiple decoded images stored in a second DRAM as a reference image.

Image processor

If the number of frames in a GOP of an input stream is not less than 15, the GOP is determined as a control unit time. If the number of frames in the GOP is less than 15, the following GOP is connected thereto until the number of frames becomes not less than 15 and the connected GOPs are determined as a control unit time. After correcting the control unit time, the average input bit rate Sin each control unit time is obtained, and by using information on the input stream including the average input bit rate S, a quantization step value of an output stream is calculated.

Transcoder for conversion by obtaining a period conversion factor from a bit rate ratio

The image processor includes a &#x2153; multiplier circuit that approximately multiplies an input value X by &#x2153;. The &#x2153; multiplier circuit includes a loop operation circuit that repeatedly perform a predetermined operation by loops, and a setting circuit that sets a required number of loops in the loop operation circuit. The loop operation circuit includes a register that receives an input of an input value, a bit shift circuit that performs bit shift by 2 bits to the right on a value output from the register, and an adder circuit that adds an input value and a value output from the bit shift circuit, and inputs the added value to the register.

Transcoder for converting a first stream to a second stream based on a period conversion factor

A quantization step determination part inputs an evaluation value (ACT_MB) indicating the dispersion in a macroblock and its average value (ACT_PIC). A subtracter obtains the difference between these values, and a multiplier multiplies the difference by r(&#x3c;1) to obtain a weighting value. Next, an adder adds the weighting value to an average quantization step value of source data, and finally a multiplier multiplies the sum by a step value adjustment factor &#x3b1; (&#x3e;1) to obtain a converted quantization step value (Qstep_AVC). This optimizes a bit allocation in accordance with an Activity value of the macroblock, to thereby improve the quality of image.

Growing community of inventors

Osaka, Japan

Nobuyuki Takasu