Sanyo Electric Co., Ltd.

Nobuyuki Sekikawa

Wataru Andoh

Masaaki Momen

Koichi Hirata

Tadayoshi Takada

Masaaki Anezaki

Toshimasa Sadakata

Teruo Tabata

Yoshiaki Sano

Kazuo Takeda

Noriyasu Katagiri

Nobuo Itoh

Chikao Fujinuma

Yasuhiro Tamada

Katsuhiro Hayasaka

Chikao Fujunuma

Shinya Enomoto

Tetsuya Kubota

A gate electrode includes a first polysilicon film remaining on a first oxide film, a part of a second polysilicon layersuperimposed on the polysilicon layer, and a part of the second polysilicon layer partially extending over second gate oxide films. Thus, the thickness of the gate electrode on the first gate oxide film is the same as that of the gate electrode of the prior art, but the film thickness tof the gate electrodeon the second gate oxide filmsA andB is thinner than the thickness tof the prior art. Therefore, the height gap hbetween the gate electrodeand the N+type source layerand the height gap hbetween the gate electrodeand the N+type drain layerbecome smaller compared to those of prior art, leading to the improved flatness of the interlayer oxide film

Method of manufacturing insulated gate semiconductor device

This invention is directed to the reduction of voltage dependence and thus allows easy design of integrated semiconductor circuits. The device is equipped with a P&#x2212; type resistance layer, in which a first voltage is applied to one end and a second voltage is applied to the other end and which is formed on the surface of an N-well region on the semiconductor substrate, a thin oxide film on the resistance layer, and a resistance bias electrode which includes the silicon layer formed on the thin oxide film. By adjusting the voltage applied to the resistance bias electrode, the voltage dependence of the resistance of the resistance layer is reduced.

Semiconductor device manufacturing method

When an element isolation film is formed by the LOCOS technique, as an underlying buffer layer of an oxidation resisting film, a pad oxidation film and pad poly-Si film are used. When an element is formed, they are used as a gate oxide film and a part of a gate electrode to relax a level difference between the gate electrode and the wiring on the element isolation film. A first poly-Si film (pad poly-Si film) is etched to leave its certain thickness to relax the level difference more greatly. In such a process, in manufacturing a semiconductor integrated circuit using the LOCOS technique, the number of manufacturing steps can be reduced and the level difference between the gate electrode on the gate insulating film and the wiring on the element isolation film can be relaxed.

Semiconductor device

A gate electrode includes a first polysilicon film remaining on a first oxide film, a part of a second polysilicon layer superimposed on the polysilicon layer, and a part of the second polysilicon layer partially extending over second gate oxide films. Thus, the thickness of the gate electrode on the first gate oxide film is the same as that of the gate electrode of the prior art, but the film thickness t of the gate electrode on the second gate oxide films A and B is thinner than the thickness t of the prior art. Therefore, the height gap h between the gate electrode and the N &plus; type source layer and the height gap h between the gate electrode and the N &plus; type drain layer become smaller compared to those of prior art, leading to the improved flatness of the interlayer oxide film

Insulated gate semiconductor device and its manufacturing method

To shorten the production process of the semiconductor device having the capacitance element. The pad oxide film ( ) and the first polycrystalline silicon layer ( ) are used as a stress buffering material at the time of formation of the element separation oxide film. These are not removed and used as the capacitance insulation film and a portion of the upper electrode of the capacitance element. Thereby, the removing process of the pad&bull;polycrystalline silicon layer, and the dummy oxidation and its removing process in the conventional example, can be omitted and the process can be shortened. Further, a problem of the impurity enhanced oxidation at the time of formation of the capacitance insulation film can be solved.

Semiconductor device having capacitance element and method of producing the same

Method of manufacturing semiconductor device and semiconductor device

To shorten the production process of the semiconductor device having the capacitance element. The pad oxide film (,) and the first polycrystalline silicon layer (,) are used as a stress buffering material at the time of formation of the element separation oxide film. These are not removed and used as the capacitance insulation film and a portion of the upper electrode of the capacitance element. Thereby, the removing process of the pad.polycrystalline silicon layer, and the dummy oxidation and its removing process in the conventional example, can be omitted and the process can be shortened. Further, a problem of the impurity enhanced oxidation at the time of formation of the capacitance insulation film can be solved.

Method of manufacturing a semiconductor device

A method of making a semiconductor integrated circuit provided with an isolating region constituted of an upper and lower isolating regions, and integrated circuit element regions is disclosed, wherein: the lower isolating region is diffused upward to a depth of a little more than half the thickness of an epitaxial layer to link with the upper isolating region prior to a doping of the upper isolating region; the doping of the lower isolating region and integrated circuit element regions, is implemented by means of ion implantation through a resist film which is capable of blocking ions implanted and in which specified doping windows have been formed in advance, and a SiO.sub.2 film is used as a reference mask in an ion implanting step, and the respective borders of the upper isolating region and the specified regions of the circuit elements is determined by self-alignment. The method has advantages that the upper isolating region can be prepared by heat-treatment for relatively short time, reducing lateral diffusion and the occupied area thereof, and slippage by masking is remarkably reduced, providing a semiconductor integrated circuit with high density.

Method for manufacturing a semiconductor integrated circuit

After a base region and a base contact region, a diffused resistance region and a pair of contact regions formed at each end of the diffused resistance region are formed, an silicon oxide film of essentially uniform thickness is formed anew on the surface of an epitaxial layer. In the silicon oxide film, a collector contact/doping window, a base contact window, an emitter contact/doping window, a lower layer electrode contact window, and a diffused resistance element contact window are formed simultaneously, then the base contact region and the diffused resistance element contact regions are shielded by a mask and a collector contact region, an emitter contact region, and a lower layer electrode contact region are doped. The method of manufacturing a semiconductor integrated circuit of the present invention has the advantages that all insulating films have a uniform film thickness, eliminates the problems of side etching when the contact windows or dopant windows are formed or of etching the element regions. It is possible to form element regions of the design size and a large margin of spacing for the isolating regions and the base region is unnecessary. A high degree of integration can be achieved.

Method for manufacturing a semiconductor integrated circuit including a

A method of fabricating a semiconductor integrated circuit comprises the steps of: forming buried layers in predetermined regions of a semiconductor substrate; forming an epitaxial layer covering the substrate and the buried layers; forming isolation regions dividing the epitaxial layer into a plurality of islands; selectively implanting ions to form a base region of a vertical bipolar transistor in a surface layer of one island and simultaneously to form a resistor region in a surface layer of another island; and selectively diffusing impurities into a surface layer of the base region, to form an emitter region of the vertical bipolar transistor.

Method of fabricating a semiconductor integrated circuit

A method of manufacturing a semiconductor integrated circuit comprises the steps of: forming an epitaxial layer covering a semiconductor substrate and buried layers; forming isolation regions dividing the epitaxial layer into a plurality of islands; forming a lower electrode region of an MIS type capacitor in one of the islands; forming a base region of a vertical bipolar transistor simultaneously with or independently from the lower electrode in another island; depositing a thin dielectric layer of the MIS type capacitor on a portion of the lower electrode region; thereafter selectively diffusing impurities into the surface layer of the base region so as to form an emitter region of the vertical bipolar transistor; and forming an upper electrode of the MIS type capacitor on the thin dielectric layer.

Growing community of inventors

Ashikagai, Japan

Nobuyuki Sekikawa