Hitachi, Ltd.

Hitachi Microcomputer Engineering, Ltd.

Hitachi, Ltd., & Hitachi Microcomputer Engineering Ltd.

Nobuyuki Sato

Shinji Nabetani

Masaaki Terasawa

Kazuaki Ujiie

Ken Uchida

Kyotake Uchiumi

A semiconductor integrated circuit device includes a semiconductor nonvolatile memory, a booster circuit which generates a high voltage required for writing the data into said semiconductor nonvolatile memory, and a control circuit. With the thus constructed device, however, various external control signals often fail to assume definite levels when the power source is closed. If an operation mode to be designated is erroneously determined to be a write operation mode due to obscure levels of the external control signals, then the write operation is executed erroneously. To prevent such an eronneous operation from developing when the power source is closed, provision is made of a power souce closure detector circuit and a suitable gate circuit. Owing to these circuits, the output of the booster circuit is prevented from being applied to the memory element from the time from when the power source circuit is closed up to the time when the read operation mode is designated by an external control signal.

Semiconductor integrated circuit device

A semiconductor integrated circuit device includes a semiconductor nonvolatile memory, a booster circuit which generates a high voltage required for writing the data into the semiconductor nonvolatile memory, and a control circuit. With the thus constructed device, however, various external control signals often fail to assume definite levels when the power source is closed. If an operation mode to be designated is erroneously determined to be a write operation mode due to obscure levels of the external control signals, then the write operation is executed erroneously. To prevent such an erroneous operation from developing when the power source is closed, provision is made of a power source closure detector circuit and a suitable gate circuit. Owing to these circuits, the output of the booster circuit is being applied to the memory element from the time from when the power source circuit is closed up to the times when the read operation mode is designated by an external control signal.

A nonvolatile memory which has both the merits of a floating gate type EEPROM and an MNOS type EEPROM and which can be written into and erased with low voltages is disclosed. Each memory element in the nonvolatile memory has a floating gate, a control gate, a gate insulator film between a semiconductor body and the floating gate, and an inter-layer insulator film between the control gate and the floating gate. The gate insulator film is made up of a very thin SiO.sub.2 film and a thin Si.sub.3 N.sub.4 film formed thereon. The charge centroid of charges injected for storing data lies within the floating gate, not within the Si.sub.3 N.sub.4 film.

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Tokorozawa, Japan

Nobuyuki Sato