Trio Kabushiki Kaisha

Nobuyuki Sanpei

Kazumasa Sakai

Isumi Shibata

A bias circuit for single-ended push-pull amplifiers permits class A or class AB operation while substantially reducing the idling current of the output transistors at low input signal levels. The bias circuit includes a DC current limiting circuit comprised of transistors that are connected between the common output of the amplifier and the bases of the output transistors. The transistors of the DC current limiting circuit limit the idling currents of the output transistors when there is no input signal applied to the amplifier. The bias circuit further includes RC/diode circuits which operate to increase or decrease the bias voltages of the transistors of the DC current limiting circuit corresponding to a decrease or an increase of the output voltage of the amplifier. In this way, the idling currents of the output transistors are changed so as to effectively follow the input signal power.

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Tokyo, Japan

Nobuyuki Sanpei