Ps4 Luxco S.a.r.l.

Elpida Memory, Inc.

Nobuyuki Sako

Eiji Hasunuma

A method of forming a semiconductor device includes the following processes. A first interlayer insulating film is formed over a cell transistor and a peripheral transistor. A cell contact hole is formed in the first interlayer insulating film, the cell contact hole reaching the cell transistor. A lower contact plug is formed at a bottom of the cell contact hole. A peripheral contact hole is formed in the first interlayer insulating film, the peripheral contact hole reaching the peripheral transistor. A first peripheral contact plug is simultaneously formed in the peripheral contact hole and an upper contact plug in the cell contact hole, the upper contact plug being disposed on the lower contact plug.

Method for forming semiconductor device

A device manufacturing method includes: sequentially forming a first sacrificial film, a first support film, a second sacrificial film, and a second support film on a semiconductor substrate; forming a hole to pass through these films; forming a crown-shaped electrode covering an inner surface of the hole and connected to the second support film and the first support film; forming a first opening in the second support film into a first pattern designed such that the connection between the crown-shaped electrode and the second support film is at least partially maintained; removing at least a part of the second sacrificial film through the first opening; forming a second opening in the first support film with use of the first opening; and removing the first sacrificial film through the second opening. This method is able to prevent misalignment of openings between the support films.

Manufacturing method of device

A semiconductor device has memory cell portions and compensation capacitance portions on a single substrate. The memory cell portion and the compensation capacitance portion have mutually different planar surface areas. The memory cell portion and the compensation capacitance portion include capacitance plate electrodes of the same structure. The capacitance plate electrode has a laminated structure including a boron-doped silicon germanium film and a metal film.

Growing community of inventors

Tokyo, Japan

Nobuyuki Sako