Hitachi, Ltd.

Other

Hitachi Software Engineering Company, Ltd.

Hitachi Video and Information System, Inc.

Hitachi Software Co., Ltd.

Nobuyuki Minowa

Akira Fujibayashi

Atsushi Tanaka

Kazuhisa Fujimoto

Hiroki Kanai

Hikari Mikami

Hisashi Nanao

Hideaki Fukuda

Yasuo Inoue

Tsutomu Koga

Masanori Fujii

Naoki Okada

Makoto Asari

Tetsuya Abe

Shuji Nakamura

Masahiro Arai

Masanori Takada

Hiromichi Fujisawa

Kenji Mori

Hidefumi Masuzaki

Masaaki Fujinawa

Satoshi Ito

Mitsuru Inoue

Naoki Moritoki

Akihisa Hirasawa

Koji Washiya

Masato Shimizu

Yoshinori Okubo

Yasuhiro Igarashi

Emi Nakamura, Legal Representative

Reduction of data processing capacity attributable to the occurrence of a failure is prevented by promptly identifying the failure location. A storage apparatus includes a plurality of expanders connected to storage media storing data sent from a host system, and a controller for controlling the expanders, wherein the controller sends a failure detection command to the plurality of expanders; the plurality of expanders store the command in their own storage units; and if one expander from among the plurality of expanders detects a failure in another expander immediately following and connected to the one expander, the one expander reads the command stored in a storage unit for the one expander and sends a response including failure detection information corresponding to the command to the controller.

System and method for failure detection by a storage expander preceding an expander experiencing a failure

The first controller includes a first relay circuit which is a circuit that controls data transfer, and a first processor coupled to the first relay circuit via a first second path. The second controller includes a second relay circuit which is a circuit that controls data transfer, and is coupled to the first relay circuit via the first path, and a second processor coupled to the second relay circuit via a second second path. The first processor is coupled to the second relay circuit not via the first relay circuit but via a first third path, and accesses the second relay circuit via the first third path during an I/O process. The second processor is coupled to the first relay circuit not via the second relay circuit but via a second third path, and accesses the first relay circuit via the second third path during an I/O process.

Storage system with multiple controllers and multiple processing paths

Provided is a storage subsystem capable of maintaining the reliability of I/O processing to a host apparatus, even if there is an unauthorized access from a processor core to a switch circuit, by applying a multi-core system to a processor. A multi-core processor is applied to a second logical address space that is different from a first logical address space to be commonly applied to multiple controlled units such as a host interface to be accessed by the processor. The switch circuit determines the processor core that issued an access based on an address belonging to a second address space, and maps an address containing in an access from the processor core to an address of a first address space.

Storage subsystem and its control method

A PLD is interposed on the communication route between a microprocessor (hereinbelow called MP) and boot memories. The boot memories store MP start-up data needed to start up the MP and start-up protection code constituting protection code for the MP start-up data. The PLD reads the MP start-up data and the start-up protection code thereof from the boot memories, performs, in hardware fashion, a check of the validity of the MP start-up data using this start-up protection code and, if a negative check result is obtained, resets the MP and if a positive check result is obtained, inputs the start-up data that is thus read to the MP.

Storage control system and boot control system

According to the present invention, in cases where a CHA function and a DKA function are mounted within a single package, a battery power supply that is used during the occurrence of power supply trouble is effectively utilized so that the supply of power can be separately controlled for each function. A CHA part and DKA part are disposed in a single control package. When trouble such as a power outage is detected, the CHA part blocks access requests from the host, and initiates end processing. When the end processing of the CHA part is completed, the package internal power supply control part stops the clock supply to the CHA part. Then, when the DKA part completes destage processing, the package internal power supply control part stops the supply of power to the DKA part. The power consumption of the package is lowered in stages in accordance with the progress of the end processing.

Storage device and storage device power consumption control method

A controller and one or more intermediate devices that are connected to a plurality of processors and this controller so that communications are possible are provided. A first access message including a designated value designated by the processor is transmitted to the controller by a first intermediate device connected to the processor. The controller specifies a local memory address corresponding to the designated value included in the first access message, and transmits a second access message including this specified local memory address to two or more other processors. The two or more other processors or second intermediate devices that are connected to these processors access local memory regions of two or more local memories respectively corresponding to two or more other processors, which are local memory regions corresponding to the local memory addresses included in the second access message.

Storage system and storage control method

A storage system includes a plurality of kinds of packages such as channel adapters, cache switches, disk adapters, basic memory boards, a shared memory, cache memories, memory board expansions and individual disk drives. Nonvolatile memories are mounted on each of those packages to store event information concerning the package on which the respective memory is mounted. In case a package is exchanged or newly installed or in case a package fails, the event information is stored in the nonvolatile memory of the package in correspondence with the packaging position information of the package in the storage system, so that this event information can be accessed at any time.

Storage of fault and position data in nonvolatile memory on system components

A disk array control device which includes a plurality of channel interface (IF) units, a plurality of disk IF units, a cache memory unit, and a shared memory unit. The connection system between the plurality of channel IF units and plurality of disk IF units and the cache memory unit is different from the connection system between the plurality of channel IF units and plurality of disk IF units and the shared memory unit. In the invention the plurality of channel IF units and the plurality of disk IF units are connected via a selector to the cache memory unit whereas the plurality of channel IF units and the plurality of disk IF units are directly connected to the shared memory unit with no selectors.

Disk array control device with two different internal connection systems

The present invention makes it possible to transfer information between processors by a method that places little burden on the reception side processors. The information processing device is a device that processes information using a plurality of processors, comprising one or more first processors that have one or a plurality of local memories, and one or more second processors that write write information directly into the local memory that the target first processor has. The second processors store address maps in which local memory addresses for the first processors are recorded; these second processors acquire local memory addresses from these address maps, and write write information into the acquired local memory addresses.

Device and method for performing information processing using plurality of processors

This invention relates to a disk array controller. There has been demand for a large scale memory device system operable without interruption. Further, in order to cope with the recent trend toward open systems, scalability of performance and capacity in such systems is needed. Conventionally, internal buses such as ones which connect the channel interface section to the shared memory section, and the disk interface section to the shared memory section, have been mounted on one platter, and the channel interface and other packages have been mounted thereon. If the internal buses have failed, the operation of the whole system must be stopped. There has been another problem that the performance of the internal buses is fixed. A disk array controller according to this invention comprises an interface platter on which a channel interface section and a disk interface section are mounted, a memory platter on which a shared memory section is mounted, and a cable which connects the interface platter to the memory platter in order to solve the above problems.

Scalable disk array controller

The invention efficiently mounts substrates to back planes and accomplishes high quality signal transfer. Connectors to which N adaptor substrates are fitted and connectors to which M bus switch substrates are fitted are provided to a multi-layered back plane. Signal pin groups of the connector on the adaptor substrate side are grouped into M data paths. Signal pins of the connector on the adaptor substrate side and corresponding signal pins of the connector on the bus switch substrate side are arranged horizontally in such a fashion as to exist on the same plane (with positions in a Z direction being substantially equal). Therefore, wiring patterns for connecting corresponding signal pins can be formed substantially linearly and a large number of substrates can be efficiently mounted to a limited area.

Fitting substrate for connection and fitting substrate for connection for use in disk array control apparatus

In a disk array control apparatus having a plurality of magnetic disk apparatus under its command for controlling data transfers to and from a host computer in a multiprocessor configuration comprising a plurality of microprocessors, a data path is provided between a cache unit and a shared memory unit, provided independent of the cache unit, for storing configurational information and the like required for system operation and control by the microprocessors, so that in the event of trouble with the apparatus or a sudden abnormality in main power supply, configurational information in a volatile shared memory unit is saved into non-volatile magnetic disk apparatuses from the data path via the cache unit by utilizing an uninterrupted power supply apparatus (UPS).

Storage system including a storage control apparatus which controls operation of the system based on control information stored in shared memory

Scalable disc array controller

Growing community of inventors

Odawara, Japan

Nobuyuki Minowa