Nec Electronics Corporation

Renesas Electronics Corporation

Nobuyuki Katsuki

Hirofumi Nikaido

Michihiro Kobayashi

Yasuhiro Kawakatsu

Noriyuki Ota

Hitoshi Abiko

A semiconductor memory includes a DRAM having, as seen in planar view, a first bit line and a second bit line formed on a first active area, a first cell contact formed on the first active area, and a first capacitor contact formed on the first cell contact and which is connected to a capacitor. As seen in planar view, the first cell contact is positioned closer to the second bit line than to the first bit line, and the first capacitor contact is formed offset in a direction approaching the first bit line with respect to the first cell contact.

Semiconductor memory

Two interconnect layers are electrically connected while reducing the number of manufacturing steps. A contact plugwhich is formed into a beaded shape in a layer underlying two interconnectsC andD and which also electrically connects the two interconnectsC andD is included. The two interconnectsC andD are separated to each other and are formed in a same layer. The contact plugis simultaneously formed with a contact plugto be connected to an interconnectand a contact plugto be connected to a source/drain region

Semiconductor device with a contact plug connected to multiple interconnects formed within

A lower electrode projects outward from a common end face of an upper electrode and a capacitor film. A protective film, which is made of a different material from the capacitor film, is deposited on top of a part of the lower electrode outside the end face. The protective film also extends to the position at a certain distance inward from the end face, so that it is placed between the capacitor film and the lower electrode. The capacitor film thereby has a stepped surface near the end face due to the presence of the protective film, which suppresses the progress of damage during etching of the upper electrode and the capacitor film. Further, the protective film prevents the occurrence of damage in the lower electrode.

Semiconductor device

The semiconductor device has a fuse and a fuse opening created above the fuse. The fuse is divided into a plurality of lines at a crossing portion where the fuse crosses with an edge of the fuse opening. The plurality of divided lines of the fuseare in parallel with each other and in perpendicular to the edge of the fuse opening.

A semiconductor apparatus includes an internal layer where a first power supply line to provide a first power supply to transistors in a layout cell and an internal cell line to connect transistors in the layout cell are placed, an input/output line connected with an input/output terminal of the layout cell is placed, and a shield line which is placed between the internal layer and the input/output line so as to cover the internal layer and the first power supply line.

Semiconductor apparatus having shield line provided between internal layer and input/output line in layout cell

When a top surface area for a plurality of dummy patterns and a width for a plurality of trenches are set on the basis of a ratio (an occupation density of the film for polishing in an adjacent region ) of a total top surface area for raised sections of the film for polishing to a horizontally projected area of the adjacent region it is possible to suppress dishing and erosion and thereby attain a high planarity when a film for polishing is formed on a semiconductor substrate, wherein dummy patterns partitioned by a plurality of trenches are disposed in an element isolation region and planarization by the CMP is applied thereto.

Growing community of inventors

Kanagawa, Japan

Nobuyuki Katsuki