Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Electric Corporation

Nobuyuki Kasai

Takuji Sonoda

Shinichi Sakamoto

Tetsuya Yagi

Tomoki Oku

Shinichi Miyakuni

Yasutaka Kohno, Deceased

First and second semiconductor lasers interelement-separated from each other are formed. Total thickness of a fourth upper cladding layer and a second contact layer of the second semiconductor laser is smaller than total thickness of a second upper cladding layer and the first contact layer of the first semiconductor laser. First and second ridges are formed in the first and second semiconductor lasers by dry etching, using a resist as a mask, and the dry etching is stopped when a second etching stopper layer is exposed at the second ridge. The second upper cladding layer remaining on a first etching stopper layer at the first ridge is selectively removed by wet etching, using the resist as a mask.

Method for manufacturing monolithic semiconductor laser

A resin-encapsulated semiconductor device includes a semi-conductor substrate having a surface including an insulating film and an electroplated transmission line. To avoid a possible separation and/or peeling of the insulating film with respect to the substrate, a gap is present between the insulating film and the plated line.

Semiconductor device including an insulative layer having a gap

A method of making a semiconductor device includes forming a recess in a compound semiconductor substrate using a patterned insulating film on a surface of the substrate, implanting dopant ions at the bottom of the recess to form a channel region, and depositing a refractory metal film. The refractory metal film is etched, using a resist pattern, to form a gate electrode and additional dopant ions are implanted to form relatively highly doped regions intersecting the channel region. Very highly doped regions are formed my implantation, after removing the insulating film, using the gate electrode and remainder of the resist mask as an implantation mask. After stripping the resist, annealing to activate the implanted ions, and depositing a passivating film on the substrate and gate electrode, source and drain electrodes are formed. The field effect transistor thus produced has a high breakdown voltage, improved reliability, a highly controlled pinch-off voltage, and improved transconductance and operating speed.

Method of fabricating semiconductor device

A semiconductor device includes a compound semiconductor body having a recess, the recess having a bottom and a hollow, and a refractory metal gate electrode having a lower portion within the hollow. The compound semiconductor body includes a compound semiconductor substrate; a channel layer including a compound semiconductor of a first conductivity type, the channel layer being located on the substrate between the gate electrode and the substrate; first active layers of the compound semiconductor and of the first conductivity type located on regions of the substrate in the recess where the channel layer is not present; and second active layers of the compound semiconductor and of the first conductivity type located on regions of the substrate in the recess where the channel layer is not present; and second active layers of the compound semiconductor of the first conductivity type located on regions of the substrate sandwiching the recess. Therefore, the controllable region in the channel layer is not adversely affected by a depletion layer produced at the interface between the first active layers and a passivation film, whereby an unwanted reduction in the control speed in the channel layer due to the charging and discharging of carriers in traps at the interface is avoided.

Recessed gate field effect transistor

A semiconductor device includes a drain electrode, a source electrode, and a gate electrode on a semiconductor substrate; a semiconductor layer on a region of the semiconductor substrate and including a first dopant concentration region on which the gate electrode is centrally disposed; a second dopant concentration region more heavily doped than the first dopant concentration region, disposed adjacent the first dopant concentration region and having a length toward the drain electrode; third dopant concentration regions, more heavily doped than the second dopant concentration region, respectively disposed adjacent the second dopant concentration region at drain side and adjacent the first dopant concentration region at the source side; a drain electrode disposed on one of the third dopant concentration regions; and a source electrode disposed on the other of the third dopant concentration regions. Even when the second dopant concentration region is etched while producing a sidewall in producing the semiconductor device, the depth of the surface depletion layer on the etched part is shallow so that channel confinement is relaxed. In addition, even when an electric field is concentrated toward the drain side of the first dopant concentration region, the electric field at the third dopant concentration region is relaxed.

High breakdown voltage field effect transistor

A mushroom-shaped gate electrode has a lower end in a recess in a semiconductor active layer on a semiconductor substrate. The gate electrode has an enlarged head. A metallic side wall is disposed on a portion of the leg of the gate electrode adjacent the head. Thus, the gate length of a semiconductor device, such as a field effect transistor, is reduced while the effective cross-sectional area of the gate electrode is increased whereby the noise characteristics of the semiconductor device are improved.

Method of making a mushroom-shaped gate electrode of semiconductor device

A field effect transistor includes a GaAs substrate on which an undoped GaAs layer is disposed. A doped electron supply layer is disposed on the undoped GaAs layer and has a negligible deep dopant level. A channel layer disposed on the electron supply layer has a larger electron affinity than the electron supply layer. The electron supply layer and the channel layer form a heterojunction. A third semiconductor layer having the same conductivity type as the electron supply layer is disposed on the electron supply layer. Gate, drain, and source electrodes are disposed on the third semiconductor layer. The dopant concentration of the third layer is smaller than the dopant concentration of the electron supply layer.

Field effect transistor

Semiconductor device with a mushroom-shaped gate electrode

At least two unit transistor groups, each including unit transistors arranged along a straight line, are disposed on a substrate parallel to and facing each other. Each transistor in one group and a facing transistor in the other group have integral first, second, and control electrodes. The first, second, and control electrodes of the unit transistors are connected to associated respective electrode pads.

Growing community of inventors

Itami, Japan

Nobuyuki Kasai