Fujitsu Corporation

Nobuyuki Iwasaki

Toru Tsuruta

Ritsuko Tanaka

Yuji Nomura

Ryuta Tanaka

Teruo Ishihara

Norichika Kumamoto

Yoshinari Sugimoto

Kazuaki Yoshida

Masashi Shibata

Koki Fujimoto

Atsuyoshi Koga

Kouki Kurokawa

A relay device has a plurality of input/output modules each having input/output ports, each input/output module including throughput measuring means for measuring throughput of communication packets received from other input/output modules, and throughput limiting means for limiting throughput of communication packets to be transferred to the other input/output modules on the basis of the throughput measured by the throughput measuring means, wherein the relay device transfers communication packets between the input/output modules to relay the communication packets.

Relay device and band controlling method

When a plurality of pre-stage packet controllers receive an instruction on transmission of the priority information from a post-stage packet controller, they derive priority information on the basis of the ratios of bandwidths which can be used at minimum by the user devices, and statuses of storing packets in the buffers, and transmit the priority information to the post-stage packet controller. The post-stage packet controller then selects a pre-stage packet controller to be actually given packet transmission permission on the basis of the priority information received from the plurality of pre-stage packet controllers, and transmits an instruction on packet transmission permission to the selected pre-stage packet controller. The pre-stage packet controller which has received the instruction on packet transmission permission from the post-stage packet controller then transmits a packet to the post-stage packet controller.

Bandwidth control system, method, and program storage medium storing program thereof

A packet sending apparatus that improves packet transmission quality by preventing loss of packet information, while minimizing a reduction in transmission rate. A clock frequency deviation correction calculation section calculates a valid packet sending period in which valid packets packet information of which is not lost due to clock frequency deviation between the packet sending apparatus and a packet receiving apparatus are included and the number of valid packets included in the valid packet sending period. A packet sending section exercises priority control by determining whether a packet to be sent is a priority packet or a non-priority packet and by sending a priority packet in preference to a non-priority packet, and performs a packet sending process on a packet to be corrected other than the valid packets completely included in the valid packet sending period at the time of correcting the clock frequency deviation by inserting a packet gap corresponding to a sending stop period for which packet sending is stopped to prevent loss of packet information.

Packet sending apparatus and packet transmission system

The present invention relates to a multiprocessor system, which comprises two or more processor elements to be executed by a common program, a control section for switching such plural processor elements one from another for execution by the common program, and a storing section storing handover information relating to the common program which information is to be handover from the one processor element to the another processor element. This not only optimizes each of the functions of the processor elements, but also achieves certain delivery or interchange of the information between these process or elements, and even reduces the power consumption.

Multiprocessor system, multiprocessor control method, and multiprocessor control program retaining computer-readable recording medium

A microprocessor capable of executing a process instruction having at least one RISC type instruction is constructed to include an instruction decoding section for decoding a microcode including information which indicates transfer contents of input and output data and address information which indicates a storage location of the process instruction, a data reading section for reading input data corresponding to the information which indicates the transfer contents of the input and output data decoded by the instruction decoding section and reading the process instruction corresponding to the address information, and an operation process executing section for implementing one or a plurality of operation unit resources capable of executing an operation process according to the input data read by the data reading section and the process instruction.

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Fukuoka, Japan

Nobuyuki Iwasaki