Mitsubishi Denki Kabushiki Kaisha

Kabushiki Kaisha Toshiba

Matsushita Electronics Corporation

Nobuyuki Ikeda

Takenobu Iwao

Miho Yokota

Hiroshi Sakurai

Shuichi Kato

Hirotaka Toya

Ikuko Osajima

Katsumasa Jin

Akira Suzuki

Junji Michiyama

Toshihiro Morohoshi

Yuuji Umeda

Shinji Yajima

Hiroshi Fujimoto

Yukari Murata

Hirokazu Yamamoto

Yoshiaki Arima

Akehiro Watabe

Toshinori Otsuka

Tatsuhiro Nishioka

Yoshito Kobayashi

Satoko Takada

Shinji Ogishima

Yoshihiro Takahashi

A non-transitory, computer-readable medium stores a software component that includes a fraud examination module. The fraud examination module restricts a use of the software component if the use is unauthorized. The fraud examination module includes fraud determination data which predefines use conditions. The fraud examination modules also includes a determination module that obtains use data and determines the use of the software component to be unauthorized if the obtained use data does not match the use conditions. The use conditions predefined by the fraud determination data include a device identification number which is unique to a device on which an installation of the software component is permitted. The determination module obtains, through an operating system, a device identification number which is unique to a device on which the software component is actually installed as the use data.

Software component, software component management method, and software component management system

A viewing area adjusting device has an image pickup unit capable of shooting a forward direction of a stereoscopic video display device capable of displaying a stereoscopic video, a viewer information detector configured to detect the number of viewers and positions of the viewers by a video shot by the image pickup unit, a viewing area adjustment policy determining unit configured to select any one of a plurality of viewing area adjustment policies based on the number of viewers detected by the viewer information detector, a viewing area information computing unit configured to compute an adjustment amount for the viewing area, and a viewing area adjusting unit configured to adjust the viewing area.

Viewing area adjusting device, video processing device, and viewing area adjusting method based on number of viewers

It is possible to leave records with which analysis of a cause can be efficiently performed when a trouble occurs in an observation target system and realize reduction in the size of the records at the time of recording. The present invention is proposed as a log recording apparatus. This log recording apparatus is provided with: a cell number storage unit to store a cell number table with cell numbers, each being data for identifying a cell number from a state/event combination; a cell number generation unit acquiring data indicating an event and a state from an observation target system, to determine a cell number corresponding to the event and the state with the use of the cell number table stored in the cell number table storage unit and the data indicating the event and the state; a log data generation unit to generate log data which includes the cell number determined by the cell number generation unit; and a log data recording unit to record the log data generated by the log data generation unit.

Log recording apparatus

A network communication system has terminal devices belonging to a group, the terminal devices generating, if there is a leaving terminal device leaving from the group, an updated group encryption key corresponding to a new group encryption key, from a deletion key corresponding to the leaving terminal device and a group encryption key, and, after the leaving terminal device leaves the group, communicating by using the updated group encryption key; and a group management server generating the updated group encryption key corresponding to the new group encryption key from the deletion key corresponding to the leaving terminal device and the group encryption key, and, after the leaving terminal device leaves the group, communicating by using the updated group encryption key.

Terminal device, group management server, network communication system, and method for generating encryption key

A software component, which enables a computer to execute processing, is delivered from a management department and includes at least one software module executable by the computer; a first software subcomponent configured to transmit a component identifying information for identifying the software component, to a software component managing server when the software module is executed; and a second software subcomponent configured to transmit a device identifying information for identifying the computer on which the software component is executed, to the software component managing server when the software module is executed.

Software component and software component management system

In designing an integrated circuit, low-order blocks are arranged in a formation area of a high-order block in a core area with small spacing. Arrangement of and wiring between cells are performed in the low-order blocks. Input/output terminals used for connection between the cells also serve as signal connection terminals of the low-order blocks. Connection between the low-order blocks is performed by connecting the input/output terminals to each other with signal connection wiring. The signal connection wiring is constituted by a wiring layer and a via through a high-order block. The wiring layer and via constituting the signal connection wiring are different from the wiring layer and via used for connection between cells in low-order blocks.

Method of designing hierarchical layout of semiconductor integrated circuit, and computer product

In a semiconductor integrated circuit, the number of rows of transistors in each of first driver circuits is increased or decreased using MOS transistors group in clock driver circuits regions arranged in an array, such as in portions of circuit cell regions into which a core region is divided, in order to supply clock signals to cell, such as a megacell, through a mesh of interconnected clock signal supply lines, in the core region.

Semiconductor integrated circuit device and method of laying out clock driver used in the semiconductor integrated circuit device

A macro cell of field effect transistors includes source-drain areas respectively divided into a contact area and a non-contact area. One source-drain area of two of the source-drain areas located on opposite sides of the effective width portion of a gate electrode has a contact area at an upper portion and a non-contact area at a lower portion while the other source-drain area has the non-contact area at its upper portion and the contact area at its lower portion. The distance between effective width portions of gate electrodes where the non-contact area is located is smaller than the distance between effective width portions of gate electrodes where the contact area is located.

Macro cell

A control program generating apparatus for generating a control program, comprises means for storing a plurality of control filter components corresponding to a plurality of partial specifications, respectively; priority designation means for designating the priority of each of the partial specifications, and generating means for combining the control filter components corresponding to a plurality of the partial specifications on the basis of the priority designated by the priority designation means.

Apparatus and method of generating control program

Connection between a PMOS transistor and an NMOS transistor is made through a refractory metal salicide layer in the source and drain regions of these transistors. The salicide is low in resistance, thereby partially substituting for a first Al wiring in intracell wiring. The resulting empty area provides a wiring area and, hence, the freedom of chip layout is enhanced. Besides, in a microcell which constitutes a logic circuit, such as a gate array, lateral wiring grid dots can be utilized as a wiring area.

Field effect transistor array including refractory metal silicide

A plurality of macro cell layout regions 9 in cell regions 2 on a semiconductor substrate 1 are divided into three portions in a second direction. Each of the divided portions is provided with basic circuits 14a through 14c. In each basic circuit, a first common line 16 is connected to an output node of a clock input driver 11 via a clock output line 17. A plurality of predrivers 15(1) through 15(n) have their input nodes IN connected to the first common line 16 and have their output nodes OUT connected to a second common line 18. A plurality of main drivers 19(1) through 19mhave their input nodes IN connected to the second common line 18 and have their output nodes OUT connected to a third common line 20. The third common line is connected to a plurality of clock signal supply lines 21(1) through 21(s) commonly provided to the basic circuits 14a through 14c. The clock signal supply lines 21(1) through 21(s) are connected to clock input nodes of internal circuits 22 each requiring a clock signal.

Clock driver circuit and semiconductor integrated circuit device

A clock driver circuit is furnished in a centrally located macro cell layout region. The clock driver circuit has a plurality of predrivers and a plurality of main drivers. The input and output nodes of the predrivers are short-circuited by a first and a second common line, and the input and output nodes of the main drivers are short-circuited by the second and a third common line. A plurality of clock driver circuits are formed predetermined distances apart and arranged to intersect the clock driver circuit perpendicularly. Each of the clock driver circuits has a plurality of predrivers and a plurality of main drivers. The input and output nodes of the predrivers are short-circuited by a fourth and a fifth common line, and the input and output nodes of the main drivers are short-circuited by the fifth and a sixth common line. The third and the fourth common lines are interconnected. The sixth common line is connected to clock signal supply lines which in turn are connected to a plurality of second macro cells.

Clock driver circuit in a centrally located macro cell layout region

This invention offers a font processor which performs thinning processing, standard processing and bolding processing in outline font according to a resolution level of an output apparatus. According to this invention, a rasterizer generates a raster image in a first area from the outline font, which is stored in a font memory. An outline producer produces an outline image in a second area according to an outline width, which is determined by an outline width determiner. An operation unit makes an logical operation of the raster image and the outline image, and generates an thinned or bolded raster image.

Apparatus and method for font thinning and bolding based upon font

A documentary information processing system for creating and editing a multimedia document. Document files are correspondingly associated with icons symbolizing them. Likewise, partial areas provided within a document are correspondingly associated with icons symbolizing them. On a screen, information (texts, graphs, etc.) within a partial area is deleted and replaced by an icon. The icon is clicked for activation to return the information of the partial area symbolized by the icon onto the screen. There are two printing modes, that is a mode allowing the icon to be printed as it is, and a mode printing original information symbolized by an icon. It is possible to edit a document in editing units of icons. Interrelation can be defined among a plurality of icons.

System and method for processing document information using password

In an EEPROM, source electrodes S of memory cell transistors MT1 to MTn are grounded, via transistors MG1 to MGn. The source electrodes S are separated from each other so as to maintain the source electrode S of each of the memory cell transistors MT1 to MTn at an open state, even when a leak path is formed by the memory cell transistor MTi in the written state (low threshold voltage). In the EEPROM, an EPROM circuit in which the write operation can be continuously performed without the erase operation can be obtained. Further, an EEPROM circuit having the nonerasable region (the region which functions as the EPROM) and the erasable region (the region which functions as the EEPROM) can be also provided.

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Fuchu, Japan

Nobuyuki Ikeda