Panasonic Corporation

Panasonic Intellectual Property Management Co., Ltd.

Socionext Inc.

Nobuyuki Ichiguchi

Tetsuji Mochida

Takao Yamaguchi

Atsushi Yoshida

Tomoki Ishii

Takaharu Tanaka

Satoru Tokutsu

Takashi Yamada

Ryuta Nakanishi

Koji Asai

Daisuke Imoto

A bus system () for a semiconductor circuit transmits data on a networked bus between a first node and at least one second node via a relay device () arranged on the bus. The bus system () includes a first bus of a low delay and a second bus of a high delay. The first node generates a plurality of packets by attaching, to the data stored in a buffer (), information specifying a priority of transmission. The relay device () converts a priority based on a priority conversion rule, which is determined based on a transmission delay of the high-delay bus, allocates a buffer of a destination relay device to which each packet is to be sent, based on the converted priority, and sends packets in a descending order. The relay device () stores packets in a buffer () based on the priority.

Bus system and computer program

An exemplary interface apparatus according to the present disclosure connects together an initiator and a packet exchange type bus network formed on the integrated circuit. In the bus network, if the initiator has submitted request data with a deadline time specified, the initiator receives, by the deadline time, response data to be issued by a node in response to the request data. The interface apparatus includes: a correcting circuit which corrects the deadline time of the request data according to the timing when the request data has been submitted, thereby generating corrected deadline time information; a header generator which generates a packet header that stores the corrected deadline time information; and a packetizing processor which generates a request packet based on the request data and the packet header.

Interface apparatus and memory bus system

The access controller conducts arbitration between first nodes, each of which is attempting to transmit data to any of second nodes as destinations through a network of buses. The access controller includes: a buffer which receives the data that have been provided by the first nodes with mutually different required qualities and destinations, classifies the data according to their destinations and required qualities, and stores the classified data separately; an inter-class arbitrator which sequentially selects one of the required qualities of the data after another in the order of their severity; an inter-destination arbitrator which selects the destinations of the data to be transmitted and gets the transmission quantities of the data distributed among the destinations; and a transmission controller which controls transmission of the data based on the required qualities selected by the inter-class arbitrator and the destinations selected by the inter-destination arbitrator.

Access controller, router, access controlling method, and computer program

A command processing apparatus that processes a plurality of commands which are issued independently from a first master and a second master is provided. The command processing apparatus sequentially issues commands to a storage apparatus including a plurality of banks. The first master issues a first command and a second command in order to the command processing apparatus, with the first command being a command to request access to a first bank and the second command being a command to request access to a second bank different from the first bank. When the second master issues a third command to the command processing apparatus during an interval between issuance of the first command and the second command, the command processing apparatus issues the second command to the storage apparatus consecutively after the first command by prioritizing the second command over the third command.

Command processing apparatus, method and integrated circuit apparatus

A command processing apparatus and method are provided for optimally processing commands issued asynchronously from a plurality of masters to a storage apparatus including a plurality of banks, where each master issues commands for a bankand a bankalternately. The command processing apparatus includes buffer units that obtain commands issued from the plurality of masters, an arbitration unit that arbitrates the obtained commands, and an issuance unit that issues commands to the storage apparatus according to the arbitration. The arbitration unit reads the commands of the plurality of masters obtained in the buffer units, and selects one command as a result of arbitration. The arbitration unit waits until a next command of a master relating to the selected command becomes readable, and reads the next command. The issuance unit consecutively issues the selected command and the read command to the storage apparatus.

The memory control device according to the present invention includes a command generating unit which divides the memory access request issued by the master into access commands each of which is for one of the memory devices, a command issuing units which issue each of the access commands to the memory devices, a data control unit which switches data between a master and memories, and the command generating unit switch between control for outputting an identical physical address to the memory units and control for outputting different physical addresses to the memory devices, depending on when the physical addresses of the memory devices are identical and when the physical addresses of the memory devices are different, each of the memory devices corresponds to one of the divided access commands.

Memory control device, memory device, and memory control method

The information processing device in the present invention includes a memorywhich is a DRAM featuring a burst mode, and burst-transfers data at successive column addresses, masters (), (), and () which issue access requests, and a command processing unit () which converts an access address that is included in the access request issued from each master. One or more of the masters access an M&#xd7;N rectangular area where M and N are integers, and the command processing unit () converts access addresses so that a column address of data at the (K+m)th column, where K and m are integers and m&#x2266;M, of an Lth line, and a column address of data at a Kth column of an (L+n)th line, where L and n are integers and n&#x2266;N, become successive.

Growing community of inventors

Osaka, Japan

Nobuyuki Ichiguchi