Nec Corporation

Nippon Electric Co., Ltd.

Nobuyuki Hayama

Yuji Takahashi

Hironobu Miyamoto

Yuji Ando

Tatsuo Nakayama

Masaaki Kuzuhara

Yasuo Ohno

Kensuke Kasahara

Kazuaki Kunihiro

Kouji Matsunaga

Kohji Matsunaga

Susumu Ito

Naotaka Iwata

Norio Goto

Koji Matsunaga

Morimasa Nagao

Kouji Azuma

Toshio Yamagata

Group III nitride semiconductor device of field effect transistor type having reduced parasitic capacitances

A hetero-junction FET has an intermediate layer including n-type-impurity doped layer between an electron supply layer and an n-type cap layer. The intermediate layer cancels the polarized negative charge generated between the electron supply layer and the n-type cap layer by ionized positive charge, thereby reducing the barrier against the electrons and source/drain resistance.

Hetero-junction field effect transistor having an intermediate layer

A semiconductor device is provided with a plurality of hetero junction bipolar transistors arranged in a specified direction. Also, the semiconductor device comprises emitter wiring connected to each emitter of the plural hetero junction bipolar transistors, collector wiring connected to each collector of said plural hetero junction bipolar transistors, and base wiring connected to at least one base of said plural hetero junction bipolar transistors. Bases that are not connected to the base wiring among the bases of the plural hetero junction bipolar transistors are connected to the emitter wiring.

Semiconductor device, semiconductor integrated circuit, and method for manufacturing semiconductor device

A carrier travel layer is formed on the substrate of a semiconductor device with a buffer layer interposed, and a spacer layer and carrier supply layer are then formed on this carrier travel layer. On the carrier supply layer are provided a source electrode and a drain electrode, and a gate electrode is provided on an interposed Schottky layer. The carrier supply layer is composed of AlGaN and has tensile strain. The Schottky layer is composed of InGaN and has compressive strain. A negative piezoelectric charge is induced on the carrier supply layer side of the Schottky layer, and a positive piezoelectric charge is induced on the opposite side of the Schottky layer, whereby a sufficient Schottky barrier height is obtained and leakage current is suppressed.

Semiconductor device with schottky electrode having high schottky barrier

A semiconductor device of the present invention comprises Al Ga N layer and Al Ga N layer having different Al contents as an electron supply layer on GaN layer 6 serving as an active layer. An area where Al Ga N layer is formed is used as a low resistance area, while an area where Al Ga N layer is formed is used as a high resistance area. As a result, a distribution of two-dimensional electrons serving as carriers is produced within a horizontal plane perpendicular to the thickness direction of the layers to form a desired device configuration. For example, when the configuration is applied to a transistor configuration, a channel concentration under a gate is reduced to improve withstand voltage between the gate and a drain, and at the same time, a channel concentration in source and drain areas is increased to realize low contact resistance.

Semiconductor device

In a method of manufacturing a semiconductor device, trench sections are formed on a side of one of opposing surface portions of a substrate. At lest a part of each of the trench sections is covered by a power supply metal layer which is formed on the one surface portion of the substrate. The substrate is fixed to a support such that the one surface of the substrate fits to the support. A chip is separated from the substrate using the trench sections. A conductive film is formed on side surface portions of the chip and the other surface portion of the chip. Then, the chip is separated from the support.

Method of manufacturing semiconductor device with sidewall metal layers

An object of the present invention is to improve, in a group III nitride semiconductor device, the productivity, heat radiation characteristic and performance in the element high speed operation; upon a sapphire substrate in which an A plane (an (11-20) plane) is set to be the basal plane, an epitaxial growth layer of a group III nitride semiconductor is formed and, thereon, a gate electrode a source electrode and a drain electrode are formed; these electrodes are disposed in such a way that a direction along which they are laid makes an angle within 20&deg; with respect to a C axis of sapphire.

Semiconductor device having drain and gate electrodes formed to lie along few degrees of direction in relation to the substrate

A pressure sensor comprises essentially magnetoresistive elements formed on a diaphragm serving as a stress magnifier. The diaphragm may be made, for example, of glass in a thickness of 0.5 millimeter, and the magnetoresistive elements can be formed thereon in any desired pattern of thin stripes by ordinary thin-film techniques. Such sensor elements can be mass produced, e.g., by vapor deposition and etching on a large sheet of diaphragm material and cutting into chips of desired shape and size.

Magnetoresistive pressure-sensing device for automotive electronic

Growing community of inventors

Tokyo, Japan

Nobuyuki Hayama