Sandisk Technologies Inc.

Nobuyuki Fujimura

Satoshi Shimizu

Shunsuke Takuma

Takashi Kudo

Zhixin Cui

Takumi Moriyama

Tatsuya Uryu

A memory device includes at least one alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the at least one alternating stack, and a memory opening fill structure located in the memory opening and containing a vertical stack of memory elements and a vertical semiconductor channel. The memory opening fill structure includes a lateral protrusion having a tapered sidewall surface; and one of the electrically conductive layers is a taper-containing electrically conductive layer that is located at a level of the lateral protrusion of the memory opening fill structure.

Three-dimensional memory device including a dummy word line with tapered corner and method of making the same

A memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a substrate, a memory opening vertically extending through the first alternating stack and having a tapered sidewall surface at a level of one of the first electrically conductive layers, and a memory opening fill structure located in the memory opening and comprising a vertical stack of memory elements and a vertical semiconductor channel. One of the first electrically conductive layers includes a taper-containing electrically conductive layer that is located at a level of the lateral protrusion of the memory opening and has a contoured sidewall having a tapered sidewall segment that is parallel to the tapered sidewall surface of the lateral protrusion.

An alternating stack of insulating layers and spacer material layers is formed over a substrate. A plurality of arrays of memory opening fill structures is formed through the alternating stack. A plurality of dielectric plates is formed, which laterally surrounds a respective array of memory opening fill structures. Self-aligned drain-select-level isolation structures are formed between a respective neighboring pair of arrays of memory opening fill structures through gaps between neighboring pairs of the dielectric plates into a subset of layers within the alternating stack. Drain side select gate electrodes are provided from a divided subset of the spacer material layers.

Three-dimensional memory device including self-aligned drain-select-level isolation structures and method of making thereof

A bonded assembly includes a first memory die containing a first three-dimensional memory device, a second memory die containing a second three-dimensional memory device, and a support die bonded to the first memory die and comprising a peripheral circuitry configured to control the first three-dimensional memory device and the second three-dimensional memory device. The first memory die includes multiple rows of first-die proximal bonding pads, multiple rows of first-die distal bonding pads, and a plurality of first-die laterally-shifting electrically conductive paths connecting a respective one of the first-die proximal bonding pads and a respective one of the first-die distal bonding pads that is laterally offset from the respective one of the first-die proximal bonding pads. The first memory die and the second memory die can have an identical layout, and electrical connections can be shifted through the first memory die by the offset distance.

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Yokkaichi, Japan

Nobuyuki Fujimura