Other

Mitsubishi Denki Kabushiki Kaisha

Fujirebio Inc.

Renesas Technology Corp.

Hokkaido University

Mitsubishi Electric System Lsi Design Corporation

Nobuyuki Fujii

Akira Yamazaki

Fukashi Morishita

Yasuhiko Taito

Mihoko Akiyama

Mako Okamoto

Mako Kobayashi

Masahisa Okada

Eiichi Ueno

Michio Nakajima

Akira Kitaguchi

Yoshiaki Uchida

Masaaki Matsuo

Kiyoyuki Shiroshima

Hiroshi Kida

Tsuyoshi Saitoh

Yoshihiro Sakoda

Katsuya Fujimura

Takashi Shirakawa

Hiroyuki Kogaki

Eiji Miyagawa

A method of immunoassay of H5 subtype influenza A virus by which the virus can be accurately assayed even in cases where a certain level of mutation has occurred in the H5 subtype influenza A virus, and a kit therefor, and a novel anti-H5 subtype influenza A virus monoclonal antibody which can be used for the immunoassay are disclosed. The antibody or an antigen-binding fragment thereof of the present invention undergoes antigen-antibody reaction with hemagglutinin of H5 subtype influenza A virus, and the corresponding epitope of the antibody or an antigen-binding fragment thereof is located in a region other than the receptor subdomain (excluding C-terminal region thereof consisting of 11 amino acids), which antibody or an antigen-binding fragment thereof does not have neutralizing activity against the influenza A virus.

Anti-(influenza a virus subtype H5 hemagglutinin) monoclonal antibody

Well bias voltages are generated in accordance with a logic power supply voltage and a memory power supply voltage. The transistor included in a control circuit in a memory core is constituted of a logic transistor manufactured through the same manufacturing steps as those for the transistors of a logic formed on the same semiconductor substrate. Well bias voltages (VBB, VPP) are applied to a back gate of this logic transistor. A memory integrated with a logic on a common semiconductor substrate is provided which allows a transistor of a control circuit therein to be manufactured through the same manufacturing process as that of the logic and allows reduction of current consumption.

Semiconductor device with multiple power sources

The clock-generating circuit for generating a clock signal, includes a ring oscillator having an odd number of inverters connected in a ring configuration. The ring oscillator is activated to generate a clock signal when an activating signal is at a first level and is de-activated to cease generation of the clock signal when the activating signal is at a second level. A latch circuit is connected to an output node of the ring oscillator, and holds a level of the output node of the ring oscillator in response to transition of the activating signal from the first level to the second level. When the activating signal is lowered from the H level to the L level, the level of the clock signal is latched such that generation of a glitch in the clock signal will be prevented from occurring.

Clock generating circuit

A VDC circuit that supplies an internal voltage VDD to an internal circuit in a normal operation forces a transistor off in a burn-in test mode through input of a test signal to suppress supply of an external power supply voltage VDDH to a node. In a burn-in test mode, an external power supply voltage lower than external power supply voltage VDDH and higher than internal voltage VDD is supplied from an external pad.

Semiconductor integrated circuit with voltage down converter adaptable for burn-in testing

With power-on detection circuits provided for a plurality of power supply voltages, a main power-on detection signal is maintained at the active state to reset an internal node while at least one of the power-on detection signals is active. In a multi-power semiconductor integrated circuit device, current consumption at the time of power-up is reduced.

Multi-power semiconductor integrated circuit device

Oscillation outputs which are different for respective detector signals output from a first detector circuit and a second detector circuit, are obtained from a first ring oscillator and a second ring oscillator respectively corresponding to the detector circuits. A selector selects and outputs one of the oscillation outputs. Accordingly, it is sufficient to provide only one pump circuit in a circuit producing a substrate bias voltage.

Substrate bias voltage generating circuit

A tuning control circuit includes fuse devices each shifting from a conductive state to an interrupted state in response to a program input from the outside, and signal driving circuits for driving the signal levels of tuning control signals in accordance with the states of the fuse devices. A reference voltage generating circuit generates a reference voltage corresponding to a reference value of a memory array voltage of a semiconductor memory device according to the invention in accordance with an electrical resistance value which is finely adjusted in response to the tuning control signals.

Semiconductor memory device including internal power circuit having tuning function

In a detector included in a VPP generating circuit in a DRAM, an external power supply potential is applied to the gate of an N-channel MOS transistor for regulating a through current of an inverter for outputting an inversion signal of an output signal of a comparator. Since a drain-source voltage of the N-channel MOS transistor can be set to be lower than a threshold voltage Vthn of the N-channel MOS transistor, an operation margin of the detector under conditions of a low voltage and a low temperature is made wider as compared with a conventional technique.

Potential detecting circuit having wide operating margin and semiconductor device including the same

Disclosed are a fused DNA sequence which comprises a DNA sequence of a heat-resistant protein, fused directly or indirectly to a DNA sequence coding a selected protein or peptide, a fused protein expressed from the fused DNA sequence, and a method for expressing the fused protein.

Fused DNA sequence, fused protein expressed from said fused DNA sequence and method for expressing said fused protein

A DRAM is provided at a portion relating to generation of a boosted potential with a filter circuit located between a detector circuit and a ring oscillator for removing a pulse-like change in level from an output signal of the detector circuit. Accordingly, temporary stop of the charge pump circuit can be prevented even when the boosted potential exceeds in a pulse-like manner the reference potential at the vicinity of the output node of the charge pump circuit, and the boosted potential can be rapidly restored to the reference potential.

Semiconductor device provided with potential transmission line

In a VDC circuit, a differential amplifier compares a first reference potential with an internal supply potential to generate a control signal according to a result of the comparison. A constant current source transistor receives at its gate a second reference potential supplied through a path different from that of the first reference potential to operate for controlling an operation current value of the differential amplifier. A drive transistor changes conductance between a node for outputting the internal supply potential and a supply potential according to the control signal.

Voltage downconverter circuit capable of reducing current consumption while keeping response rate

A capacitor (C ) is connected between a node (L) in a double boost part and the ground, and the amplitude of a repetitive pulse from the node (L) is made less than twice that of the power-supply voltage through utilization of charge and discharge of the capacitor (C ).

Semiconductor integrated circuit

A plurality of pump modules are provided, the number of pump modules to be activated is changed depending on a mode of operation, and the number of pump modules to be activated is also adjusted with the specification of interest taken into consideration. There can be provided an internal voltage generation circuit occupying a small area and readily capable of accommodating a change in specification.

Internal voltage generation circuit

A semiconductor integrated circuit device includes a reference voltage generating circuit that can be tuned without a circuit replacement when a process condition is varied. The reference voltage generating circuit is constituted such that two different circuit configurations having different temperature properties are switched by a first switch. In each of the circuit configurations, a switch control circuit in which tuning can be performed by switching a second switch generates a control signal based on a test mode and supplies the signal to the first switch for tuning. Thereafter, a fuse in the switch control circuit is blown off to generate a control signal, and reference voltage Vref is output.

Semiconductor integrated circuit device having circuit generating reference voltage

A semiconductor device includes a constant voltage generation circuit generating a constant voltage commonly to reference voltages corresponding to a plurality of internal voltages. The plurality of reference voltages are generated from the common constant voltage. Thus, the semiconductor device for generating internal voltages is implemented, which allows reduction in layout area and decrease in test time for voltage adjustment.

Growing community of inventors

Hyogo, Japan

Nobuyuki Fujii