Japan Radio Co., Ltd.

Nihon Musen Kabushiki Kaisha

Nobuyuki Adachi

Kazuo Yamashita

Akiharu Inoue

Masahiko Egawa

Masatoyo Nishibe

A delay detection circuit and a low-noise oscillation circuit using such a delay detection circuit. When the oscillation output of a VCO is to be supplied to two high frequency mixers, a .pi./2 phase shifter 24 in the front stage of one of the high frequency mixers gives a quadrature form. High frequency components are removed from the output voltage of the high frequency mixers by LPF. DC components are also removed from the output voltage of the high frequency mixers by HPF. The output voltages of low frequency mixers contain secondary phase noise components proportional to squared phase noise components and primary phase noise components proportional to the phase noise components and also depending on the delay time .tau. of a delay unit. When the output voltage of one of the low frequency mixers is subtracted from the output voltage of the other low frequency mixer, the secondary phase noise components are offset and the dependence on the delay time .tau. is removed from the primary phase noise components. The resulting voltage is used as a control voltage for the VCO (10). No voltage control delay unit or feedback loop for controlling it are required.

Delay detection circuit and low-noise oscillation circuit using the same

A class AB push-pull drive circuit has two NPN transistors Q.sub.1, Q.sub.2 and two PNP transistors Q.sub.3, Q.sub.4, the emitters of which are connected together. A constant voltage circuit maintains voltages between the bases of transistors Q.sub.1 and Q.sub.3 and between the bases of transistors Q.sub.2 and Q.sub.4 constant. A differential input voltage is applied across the bases of the transistors Q.sub.1 and Q.sub.2. The collector currents in the transistors Q.sub.1, Q.sub.3, Q.sub.2 and Q.sub.4 increase or decrease in an exponential and differential manner. When the collector currents are in their differential relationship, they are inverted and added to provide a class AB drive current and to increase the output amplitude. The symmetry can also be improved. Since any difference between signal amplification path lengths is eliminated, a differential phase between paths is less likely to be generated in the high-frequency region. Since there is no feedback or the like for class AB drive, it is difficult for any abnormal oscillation to be produced. Since the constant voltage circuits are formed by diodes, the temperature characteristics of the transistors Q.sub.1 to Q.sub.4 can be compensated. Furthermore, the class AB push-pull drive circuit can be driven by a relatively low voltage. The bipolar transistors Q.sub.1 -Q.sub.4 may be replaced by FETs.

Class AB push-pull drive circuit, drive method therefor and class AB

A programmable frequency dividing network comprises a plurality of cascade-connected programmable frequency dividing stages each of which divides the frequency of a clock pulse by two and three based on a logic level of a preset input signal used to change a variable division ratio from one to another. In addition, there is provided a gating means for determining or detecting whether or not each of the outputs of programmable frequency dividing stages of the programmable frequency dividing network after a programmable frequency dividing stage as a second stage is brought to a predetermined pattern and an instruction signal for making a decision as to the division of the division ratio by (+1) is inputted, so as to generate the output of a logic level for causing a programmable frequency dividing stage equivalent to a first stage to divide the frequency of the clock pulse by three if it is determined to be positive in the above detection process. Then, the output of the gating means is supplied to the programmable frequency dividing stage corresponding to the first stage in the programmable frequency dividing network so as to select either one of division ratios of n and (n+ 1) with respect to a programmable frequency dividing apparatus comprising the above network and the gating means.

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Mitaka, Japan

Nobuyuki Adachi