Canon Kabushiki Kaisha

International Business Machines Corporation

Other

Preferred Networks, Inc.

Mitsubishi Heavy Industries Limited

Nobuyoshi Tanaka

Tadahiro Ohmi

Seiji Hashimoto

Takao Kinoshita

Masaki Hirayama

Shigetoshi Sugawa

Toshikuni Shinohara

Tsutomu Takayama

Akihiko Tojo

Tetsuro Kuwayama

Toshio Kaji

Toshiji Suzuki

Kiyoshi Takemura

Eiji Sakamoto

Nobumasa Suzuki

Tadayuki Okada

Hiroshi Ohsawa

Naoto Kawamura

Kazuya Matsumoto

Junji Isohata

Kazuo Iizuka

Akihiro Ogura

Kiyoshi Nishino

Makoto Ogawa

Nishino Kiyoshi

Kazuyuki Harada

Kenji Saito

Hiroyuki Tanaka

Yasushi Sato

Shunichi Ishihara

Akira Suga

Akira Ishizaki

Yasuyuki Shirai

Takahisa Nitta

Hayao Ohzu

Yoshio Nakamura

Masami Tabata

Kazuhide Ino

Hiroshi Osawa

Yuzo Kato

Hisashi Nakatsui

Tadanori Harada

Mitsuo Takeda

Takahiro Kaihotsu

Masanori Mitsugi

Hiroshi Doji

Takeo Ushiki

Hideki Ina

Mahito Shinohara

Giora Biran

Susumu Matsumura

Isamu Ueno

Naoki Ayata

Shigeyuki Matsumoto

Hidetoshi Nojiri

Takuya Kawamura

Amit Golander

Toshiyuki Nakazawa

Jun Tokumitsu

Takeshi Goshima

Kei Kawase

Masaki Oie

Yuichi Handa

Yoshiyuki Sekine

Kiyoshi Iizuka

Masaya Mori

Nobuo Kawase

Osamu Ogawa

Takahiro Yamauchi

Masakatsu Ohta

Masayuki Yokota

Masaharu Ozaki

Tsuneo Suzuki

Ken Namura

Hirofumi Narita

Toshihiko Toyota

Kazunori Takayanagi

Hiroshi Dohji

Minoru Kida

Takashi Tsuzuki

Yoshiyuki Hosokawa

Kentaro Shikata

Hironori Makimura

Hisaya Tabata

Shogo Ichishiba

Goushu Tei

Hisaki Yamauchi

Prabhakar Sachan

A semiconductor device includes a first chip, a second chip, a third chip, and a fourth chip. The first chip is placed adjacent to the second chip and the fourth chip. The third chip is placed adjacent to the second chip and the fourth chip at a position different from a position of the first chip. Data of the first chip is transferred from the first chip to the third chip via the second chip. Data of the third chip is transferred from the third chip to the first chip via the fourth chip. The data transferred from the first chip to the second chip is transferred via a wiring layer formed over a silicon and placed at a position different from positions of the first chip, the second chip, the third chip, and the fourth chip.

Semiconductor device and data transferring method for semiconductor device

A semiconductor device includes a first chip, a second chip, a third chip, a fourth chip, and a substrate. The first to fourth chips are mounted on the substrate. The first chip is placed adjacent to the second chip and the fourth chip. The third chip is placed adjacent to the second chip and the fourth chip at a position different from that of the first chip. The second chip has a first transferring circuit that transfers data from the first chip to the third chip, and the fourth chip has a second transferring circuit that transfers data from the third chip to the first chip.

An operational support device sets an execution time of overfiring serving as an operation of a power generation facility at an output higher than a rated output. The device includes a life index value acquisition unit that acquires a life index value at a start time, the life index value being an index indicating a life of the power generation facility and changing in value in one direction with the output of the power generation facility; an output pattern setting unit that sets an output pattern per unit time of the power generation facility from the start time to a stop time based on the life index value such that the life index value reaches a predetermined value; and an overfiring setting unit that sets, based on the output pattern, a time in a period from the start to the stop time at which the overfiring is to be performed.

Operational support device for power generation facility

A plurality of stored data sequences that match one or more search data sequences are determined. Each of the stored data sequences of the plurality of stored data sequences comprise a plurality of data elements and the stored data sequences are stored in a content addressable memory array. A longest stored data sequence of the plurality of stored data sequences is determined using a plurality of tracing circuits. An address associated with the longest stored data sequence of the plurality of stored data sequences is determined. A count of data elements of the longest stored data sequence of the plurality of stored data sequences is determined.

Hardware compression with search string matching

A technique for register mapping in a virtual system includes preparing a register pool that includes a plurality of registers for mapping. A mapping table is prepared that has a register identifier (ID) and information related to each of a plurality of parameters that express an operational state of the virtual system for each of the registers. At the time a register access request is issued by a hardware thread, the register ID for an access target and information related to each of the plurality of parameters that express the operational state during operation is acquired. One of the registers, for which the acquired register ID and information related to each of the plurality of parameters match the register ID and information for each of the plurality of parameters within the mapping table, is set as a mapped register to be accessed per the register access request.

Register mapping

Register mapping techniques

Compression ratio improvement by lazy match evaluation on the string search CAM

Data is compressed using content addressable memory without disruption despite error using a plurality of content addressable memories to detect sequentially repeating data elements of the data. Compression information is generated for each sequence of repeating data elements that repeat for at least a compression threshold without any one of the plurality of content addressable memories generating an indication of an error for a matching content addressable memory entry. Individual data elements are output for each of the data elements that do not repeat for the compression threshold. Compression information is generated for each sequence of repeating data elements that repeat for at least the compression threshold and then generating a currently searched data element that matches the repeating data elements when any one of the plurality of content addressable memories generates an indication of an error for a content addressable memory entry that matches the currently searched data element.

Parity error recovery method for string search CAM

A method for decoding encoded data includes receiving data encoded by replacing each of a plurality of characters with bit strings. The method also includes recording, on the basis of definition information, at least one of the characters as corresponding to each of the bit lengths, and generating decode information based on the number of characters, wherein the decode information includes bit string information for sorting the bit strings in a bit length order that is a predetermined order associated with bit lengths. The method also includes, in response to receiving a particular bit length, generating character information in which the characters are sorted in the bit length order by inserting a character corresponding to the particular bit length into a position corresponding to the particular bit length in an array in which at least one of the bit lengths.

Decoding encoded data

A hybrid mechanism whereby hardware acceleration is combined with software such that the compression rate achieved is significantly increased while maintaining the original compression ratio (e.g., using full DHT and not SHT or an approximation). The compression acceleration mechanism is applicable to a hardware accelerator tightly coupled with the general purpose processor. The compression task is divided and parallelized between hardware and software wherein each compression task is split into two acceleration requests: a first request that performs SHT encoding using hardware acceleration and provides post-LZ frequency statistics; and a second request that performs SHT decoding and DHT encoding using the DHT generated in software.

Method of hybrid compression acceleration utilizing special and general purpose processors

An apparatus and method are provided for selecting a specific position from a plurality of positions in a memory to which data elements are cyclically written. A specific data element is stored in the plurality of positions. The apparatus comprises a determination unit for determining whether the plurality of positions include any position in a specific area of the memory to which data elements are written in a current cycle. The apparatus further comprises a selection unit for selecting at least one position in the specific area out of the plurality of positions as the specific position if the determination unit determines that the plurality of positions include any position in the specific area, and for selecting at least one position out of the plurality of positions as the specific position if the determination unit determines that the plurality of positions do not include any position in the specific area.

Selecting a position where data is stored

Data encoded by replacing each of a plurality of characters with bit strings is received. On the basis of definition information, at least one of the characters is recorded as corresponding to each of the bit lengths, and decode information is generated based on the number of characters, wherein the decode information includes bit string information for sorting the bit strings in a bit length order that is a predetermined order associated with bit lengths. In response to receiving a particular bit length, character information in which the characters are sorted in the bit length order is generated by inserting a character corresponding to the particular bit length into a position corresponding to the particular bit length in an array in which at least one of the bit lengths.

An image forming apparatus includes a first sheet discharge unit, a second sheet discharge unit, a switching unit configured to cause a sheet discharge destination to switch between the first sheet discharge unit and the second sheet discharge unit, a memory unit configured to store information about drying time of a print medium, a timer unit configured to determine elapse of the drying time of the printed print medium based on the information stored in the memory unit, and a control unit configured to control the switching unit to set the first sheet discharge unit to be the sheet discharge destination based on a determination of the timer unit that a drying time of a print medium discharged to the first sheet discharge unit has elapsed.

Image forming apparatus and method for controlling the same

To provide a method and the like for testing a main memory in a multi processor system, which is capable of reducing a test execution time and accordingly a start-up time as compared with the case where a single processor is used for the test. The present invention provides a method for testing a main memory (MM) in a multi processor system (MPS) including a main processor (MP) and multiple sub processors (SP) each having a DMA transfer mechanism and a local store (LS). The method and the like including: MP allocating a partial memory region (PMA) in MM to each SP; MP requesting each SP to test the allocated PMA; each SP filling LS thereof with initial data in response to receiving the request; each SP transferring the data stored in LS thereof to PMA by using a DMA transfer; each SP transferring the data stored in PMA to LS thereof by a DMA transfer; and SP testing the data in LS; and MP judging a test result on MM by putting together the tests results in response to the completion of all the tests by respective SP.

Memory testing using multiple processor unit, DMA, and SIMD instruction

Various embodiments are provided to reduce a processing time taken when plural bit lengths each assigned to plural strings are converted into plural codes. In one exemplary embodiment, in response to input of the plurality of bit lengths, a number of strings assigned each of the bit lengths, a bit length assigned to each of the strings, and a sequence number of each string in a group of strings assigned each of the bit lengths are recorded. A plurality of base codes are generated on the basis of the numbers of the strings recorded by the recording unit, the base codes each being a code used as a base for codes having the same one of the bit lengths. A plurality of codes is generated by performing in parallel a plurality of processes respectively for the plurality of strings.

Conversion of bit lengths into codes

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Tokyo, Japan

Nobuyoshi Tanaka