Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Panasonic Intellectual Property Management Co., Ltd.

Towerjazz Panasonic Semiconductor Co., Ltd.

Tower Semiconductor Ltd.

Nobuyoshi Takahashi

Fumihiko Noro

Koji Yoshida

Masatoshi Arai

Kosaku Saeki

Yoshiya Moriyama

Keita Takahashi

Hiromasa Fujimoto

Kenji Sato

Takahiko Hashidzume

Satoshi Iwamoto

Mitsunori Fukura

Yakov Roizin

Yasunori Morinaga

Ryota Sakaida

Efraim Aloni

Micha Gutman

Masataka Kusumi

Menachem Vofsy

Masahiro Oda

Ichirou Matsuo

Hisashi Yano

Avi Ben-Gigi

Yutaka Ito

Yuka Inoue

Hiroaki Kuriyama

Takahisa Ogawa

Kiyoshi Kurihara

A semiconductor device includes first and second inspection mark regions having the same pattern including a plurality of overlay inspection marks, a first element region having a portion overlapping with the first inspection mark region, and a second element region having a portion overlapping with the second inspection mark region. The first and second element regions are adjacent to each other and have different areas. The first element region includes a first pattern aligned with a plurality of first overlay inspection marks. The second element region includes a second pattern aligned with a plurality of second overlay inspection marks.

Semiconductor device and method for manufacturing same

A semiconductor device includes a first interlayer film formed on an upper surface of a substrate, a first metal wiring line, a second interlayer film, a second metal wiring line, a first via electrically connecting the first metal wiring line and the second metal wiring line, a landing pad embedded in an upper portion of the first interlayer film and penetrating the second interlayer film, and a second via penetrating the substrate and the first interlayer film from a back side of the substrate and connected to the landing pad. The lower surface position of the landing pad is different from that of the first metal wiring line.

Each imaging pixel provided in a solid-state imaging device includes a charge accumulation part which is a diffusion region formed in a substrate, a gate electrode formed lateral to the charge accumulation part on the substrate, an insulating film formed on the charge accumulation part, and a contact plug connected to the charge accumulation part so as to penetrate the insulating film and made of semiconductor. The contact plug is, at a lower part thereof, embedded in the insulating film, and is, at an upper part thereof, exposed through the insulating film. Silicide is formed on the upper part of the contact plug, and the charge accumulation part and the gate electrode are covered by the insulating film.

Solid-state imaging device and method for manufacturing the same

A solid-state imaging device includes: a semiconductor substrate; a pixel unit formed on the semiconductor substrate; and a peripheral circuit unit formed on the semiconductor substrate, at a periphery of the pixel unit, in which the pixel unit includes: a photoelectric conversion film which converts incident light into charges; and a floating diffusion which holds the charges, the peripheral circuit unit includes a transistor including a gate electrode and two source and drain diffusion regions, and the two source and drain diffusion regions have a higher impurity concentration than an impurity concentration of the floating diffusion.

Solid-state imaging device and method of manufacturing the same

The semiconductor device includes: a plurality of bit lines formed in stripes in a semiconductor substrate of a first conductivity type, each of the bit lines being a diffusion layer of an impurity of a second conductivity type; a plurality of gate insulation films formed on regions of the semiconductor substrate between the bit lines; a plurality of word lines formed on the semiconductor substrate via the gate insulating films, the word lines extending in a direction intersecting with the bit lines; and a plurality of bit line isolation diffusion layers formed in regions of the semiconductor substrate between the word lines, each of the bit line isolation diffusion layers being a diffusion layer of an impurity of the first conductivity type. The bit line isolation diffusion layer includes a diffusion suppressor for suppressing diffusion of an impurity.

Semiconductor device and fabrication method for the same

The semiconductor device includes: memory cells each having a first multilayer electrode including a first lower electrode made of a first conductive film and a first upper electrode made of a second conductive film formed one on the other with a first interface film therebetween; and a diode having a diode electrode made of the second conductive film and a second interface film as a silicon oxide film formed at the interface between the diode electrode and a substrate. The first interface film has a thickness with which electrical connection between the lower electrode and the upper electrode is maintained, and the second interface film has a thickness with which epitaxial growth between the substrate and the diode electrode is inhibited.

First, on a semiconductor region of a first conductivity type, a trapping film is formed which stores information by accumulating charges. Then, the trapping film is formed with a plurality of openings, and impurity ions of a second conductivity type are implanted into the semiconductor region from the formed openings, thereby forming a plurality of diffused layers of the second conductivity type in portions of the semiconductor region located below the openings, respectively. An insulating film is formed to cover edges of the trapping film located toward the openings, and then the semiconductor region is subjected to a thermal process in an atmosphere containing oxygen to oxidize upper portions of the diffused layers. Thereby, insulating oxide films are formed in the upper portions of the diffused layers, respectively. Subsequently, a conductive film is formed over the trapping film including the edges thereof to form an electrode.

Method for fabricating semiconductor device

A semiconductor device includes: source/drain regions formed in a semiconductor substrate; a trapping film for storing information by accumulating charges, the trapping film being formed in a region on the semiconductor substrate which includes a region on a channel region between the source/drain regions; and gate electrodes formed on the trapping film. A silicon nitride film containing carbon is formed by low pressure CVD using an organic material so as to cover the gate electrodes and a part of the trapping film which is located between adjacent gate electrodes.

Method of forming a semiconductor device having a trapping film for charge accumulation

A semiconductor device includes a memory section formed at a semiconductor substrate and including a first transistor having an ONO film that can store charges between the semiconductor substrate and a memory electrode and a first STI region for isolating the first transistor, and a CMOS section formed at the semiconductor substrate and including a second transistor having a CMOS electrode and a gate dielectric and a second STI region for isolating the second transistor. The height of the top surface of the first STI region is set equal to or smaller than the height of the top surface of the second STI region.

Semiconductor device and method for fabricating the same

A semiconductor device includes: a semiconductor region; a plurality of bit line diffusion layers formed in an upper portion of the semiconductor region and each extending in a row direction; a plurality of bit line insulating films formed on the bit line diffusion layers; a plurality of gate insulting films formed between the respective adjacent bit line diffusion layers on the semiconductor region; and a plurality of word lines each formed on the semiconductor region in a column direction and each intersecting with the bit line insulating films and the gate insulating films. Memory cells are formed at intersections of the gate insulating films and the word lines. A plurality of connection diffusion layers including connection parts electrically connected to the bit line diffusion layers are formed in the upper portion of the semiconductor region, and a level of upper faces of the connection parts is lower than a level of upper faces of the connection diffusion layers in the semiconductor region.

Semiconductor device having diffusion layers as bit lines and method for manufacturing the same

Semiconductor device

A semiconductor memory device has a memory region which is formed on a semiconductor substrate and in which a plurality of memory cells each including a memory transistor are arranged as a matrix using a plurality of impurity diffusion layers (bit lines) and a plurality of gate electrodes (word lines) intersecting each other. The gate electrode of each of the memory transistors has an upper surface thereof formed into a protruding portion which is higher in level at the middle portion than at the edge portions. A silicide layer is formed on the upper surface of the protruding portion of the gate electrode of each of the memory transistors.

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Toyama, Japan

Nobuyoshi Takahashi