Nec Electronics Corporation

Nobuteru Oh

Yoshiaki Morishita

Hiroyuki Furukawa

Tomoaki Isozaki

Yoshihiro Masumura

The semiconductor apparatus includes an upper semiconductor chip having an upper external terminal and a lower semiconductor chip having a lower bump for electrically connecting a lower external terminal and the upper external terminal. The circuit surfaces of the upper semiconductor chip and the lower semiconductor chip are electrically connected to each other via the bump. A low impedance line having lower impedance than the internal line of the lower semiconductor chip is formed on top of the lower semiconductor chip for electrically connecting the lower external terminal and the bump.

Multichip semiconductor package

The integrated circuit device includes a memory chip and a logic chip. The memory chip has memory I/O pads and test pads. The test pads are placed in line at the position outer than memory I/O pads and larger than the memory I/O pads. The logic chip has logic COC I/O pads. The logic COC I/O pads are connected to the memory I/O pads.

Integrated circuit device with multiple chips in one package

A semiconductor device includes an internal circuit area including a plurality of I/O modules, and a peripheral area receiving therein a pair of loop test lines for testing I/O buffers in the I/O modules. The internal test line extending from each of the loop test lines toward the internal circuit area includes an out-module test line formed as the topmost layer, a first in-module test line formed as the topmost layer and connected to the out-module test line, and a second in-module test line, a portion of which is formed by connecting the in-buffer test lines together.

Growing community of inventors

Kanagawa, Japan

Nobuteru Oh