Hitachi, Ltd.

Hitachi Microcomputer Engineering, Ltd.

Hitachi Ulsi Systems Co., Ltd.

Renesas Electronics Corporation

Renesas Technology Corp.

Nobutaka Nagasaki

Takashi Tsukamoto

Haruo Keida

Kozo Katayama

Takanori Yamazoe

Hiroshi Watase

Toshihiro Tanaka

Takashi Endo

Yutaka Shinagawa

Masaru Ohki

Yasuko Fukuzawa

Nobuhiro Oodaira

Masahiro Kaminaga

Junji Shigeta

Kunihiko Nakada

Takeo Kanai

Yuuichirou Nariyoshi

Takashi Tase

Eiji Yamasaki

Masatoshi Takahashi

Chiaki Terauchi

Satoshi Taira

Masaru c/o Hitachi Ltd Int Prop Gp Ohki

Masahiro c/o Hitachi Ltd Int Prop Gp Kaminaga

Takashi c/o Hitachi Ltd Int Prop Gp Endo

Chiaki c/o Hitachi Ltd Int Prop Gp Terauchi

Yasuko c/o Hitachi Ltd Int Prop Gp Fukuzawa

Kunihiko c/o Hitachi Ltd Int Prop Gp Nakada

A semiconductor processing device according to the invention includes a first non-volatile memory () for erasing stored information on a first data length unit, a second non-volatile memory () for erasing stored information on a second data length unit, and a central processing unit (), and capable of inputting/outputting encrypted data from/to an outside. The first non-volatile memory is used for storing an encryption key to be utilized for encrypting the data. The second non-volatile memory is used for storing a program to be processed by the central processing unit. The non-volatile memories to be utilized for storing the program and for storing the encryption key are separated from each other, and the data lengths of the erase units of information to be stored in the non-volatile memories are defined separately. Therefore, the stored information can efficiently be erased before the execution of a processing of writing the program, and the stored information can be erased corresponding to the data length of a necessary processing unit in the write of the encryption key to be utilized in the calculation processing of the CPU.

Semiconductor processing device and IC card

In a semiconductor integrated circuit device equipped with a flash memory and an EEPROM which are nonvolatile memories, the invention provides a technique that makes it possible to restrict an EEPROM capacity to a minimum necessary amount and reduce a chip area. Data of a minimal size required for one application program and rewritten frequently is stored in the EEPROM, and the EEPROM is configured to have a capacity of about that minimal size. Data of the same size that are respectively handled by other applications and rewritten frequently are stored in the flash memory. With respect to an application that is actually used, its data stored in the flash memory is transferred to the EEPROM and used. Data transfer between the flash memory and the EEPROM is performed if necessary. Consequently, the EEPROM capacity can be reduced and chip area reduction can be achieved.

Semiconductor integrated circuit device, IC card, and mobile terminal

It is a technological object of the present invention to provide an information processing device, a card and a card system that have a high level of security. In order to achieve the object described above, the present invention provides a data processing apparatus comprising at least a first information processing device and a second information processing device connected to the first information processing device by a signal line, the data processing apparatus having a means for changing power consumption on the signal line during transmission of a signal through the signal line in accordance with an actual state of the power consumption that would be observed when the means were not used. Furthermore, the present invention also provides another data processing apparatus comprising at least a first information processing device and a second information processing device connected to the first information processing device by a signal line wherein, between at least either the first information processing device or the second information processing device and the signal line, a signal from the first information processing device or the second information processing device can be encrypted and a signal received from the signal line can be decrypted. In addition, the present invention also provides a further data processing apparatus comprising at least an information processing device, an information memory device and a signal line connected at least to the information processing device wherein at least in an operation to store information into the information memory device, the information is encrypted, and information stored in the information memory device can be decrypted.

Information processing device, card device and information processing system

An external sync signal generated by a clock generation circuit inside a single-chip microcomputer is supplied to an external terminal of this chip. The external sync signal is necessary in an external expansion mode but not in a single-chip mode. Therefore, the external sync signal is supplied to the external terminal through a control gate while a suitable control signal is inputted to a control terminal of the control gate. According to this circuit construction, control can be made in such a manner that the external sync signal is not supplied to the output terminal in the single-chip mode. As a result, it becomes possible to prevent noise from entering a signal supplied to an adjacent pin through a coupling capacity between the external terminals in the single-chip mode, and to reduce consumed power of an output buffer circuit which is disposed between the control gate and the external terminals.

Data processor in which external sync signal may be selectively inhibited

Growing community of inventors

Kodaira, Japan

Nobutaka Nagasaki