Nec Corporation

Hitachi, Ltd.

Hitachi Microcomputer Engineering, Ltd.

Nobutaka Amano

Kimio Ooe

Katsuaki Takagi

Takashige Kubo

Tetsuro Honmura

Kaoru Moriwaki

Shunpei Kawasaki

Disclosed herein is a voltage judgment circuit comprising one or more diodes inserted in the forward direction of a judgment voltage, a current extraction section for extracting a forward current of the diodes, and a comparison section for comparing an output current from the current extracting section with a specified current value to input the comparison results. According to the voltage judgment circuit of the present invention, the discharge after the charging can be prevented to perform the voltage judgment using a low consumption current with high accuracy. A battery cell pack having the above voltage judgment circuits also performs a similar judgment.

Voltage judgment circuit and battery cell pack having the same

In a regulated power supply circuit, a 'J characteristic curve' is obtained between an output current and an output voltage. Moreover, the output current is minimized in a grounded state in which the output terminal is grounded to minimize heat dissipation so as to facilitate circuit integration. Between the input and output terminals, there are connected an output-stage transistor and a current sense resistor in series. A voltage sense circuit senses voltage between an output terminal of the transistor and a ground terminal. The current sense circuit senses the output current by the current sense resistor. The transistor has a base terminal connected to output terminals of the voltage and current sense circuits, respectively. In this configuration, when the output terminal is grounded, the output current is set independently of a current value sensed at occurrence of an excess current. This consequently lowers the power consumption of the regulated voltage circuit in the grounded state.

Regulated power supply circuit permitting an adjustment of output

An address translation apparatus which includes a memory for storing a plurality of physical addresses, and a content addressable memory unit which stores a plurality of signal pairs that correspond to the plurality of physical addresses, each of the signal paris includes a logical address that corresponds to one of the plurality of physical addresses and memory protection level data that indicates a memory protection level allocated to a memory position of the one of the physical addresses. The content addressable memory unit includes apparatus for searching a signal pair that has a logical address in coincident with a logical address being subjected to address translation and comparing memory protection level data to comparative data at a bit position which is indicated to be the bit position to be searched by mask data, in response to the logical address translation. The mask data instructs whether the bits of the stored memory protection level data are to be searched, wherein mask data is determined depending upon a memory access privilege level allocated to a program that requests address translation, and whether comparative data are to be compared with the stored memory protection level data. The content addressable memory further includes apparatus for instructing the memory to produce a physical address that corresponds to the detected signal pair.

Address translation apparatus having a memory access privilege check

A cut-off frequency automatic adjusting filter includes a plurality of filters, one of them being a reference filter, and a feedback circuit for the reference filter. The feedback circuit is formed by a subtracter, a full-wave rectifier, an integrator and an error amplifier. A square wave signal is inputted to the reference filter as a reference signal instead of a sine wave signal in the conventional filter. The feedback circuit generates an electrical signal which causes the cut-off frequency of the reference filter and another filter to be constant.

Cut-off frequency automatic adjusting filter

In a logic simulation method for performing logic simulation of a logic circuit including a circuit with unknown internal logic, the circuit itself with the unknown internal logic is used. The internal status of the circuit is set at an objective status using the interrupt operation afforded by the circuit and thereafter, input signal value is applied to the circuit to obtain a resultant output. For other logic circuits without unknown internal logic, software logic simulation is performed. During such software logic simulation, the actual circuit with unknown internal logic is called.

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Tokyo, Japan

Nobutaka Amano