Micron Technology Incorporated

Canon Kabushiki Kaisha

Mitsubishi Electric Corporation

Elpida Memory, Inc.

Nobuo Yamamoto

Donald M Morgan

Takamasa Suzuki

Jongtae Kwak

Yasushi Matsubara

Victor Wong

Yusuke Jono

Yosuke Fujimori

Hideaki Nakano

Syohei Abiko

Yasumichi Suzuki

Mitsuru Kurita

Toshiyuki Kitamura

Koichi Ishimoto

Kyoko Nomura

Syuichi Iwata

Tsukasa Takagi

Takayuki Hanaki

Masanori Tsujihara

Methods, systems, and devices for error control for memory device are described. A memory device may be configured to perform memory management operations including error control operations. For example, a memory device may be configured to perform an error control operation on data stored in a first memory cell coupled with a source row of a memory array. The memory device may be configured to write the data to a second memory cell coupled with the target row of the memory array based on performing the error control operation on the data and determine whether the management operation is complete based at least in part on the first column address of the first memory cell. The memory device may also generate an output signal to perform the error control operation on a third memory cell coupled with the source row based on determining whether the management operation is complete.

Error control for memory device

Methods, systems, and devices for system and method for reading and writing memory management data through a non-volatile cell based register are described. A memory device may include a set of latch units addressable via a set of row lines and a set of column lines. Each latch unit may include a sense amplifier coupled with a first line and a first non-volatile capacitor coupled with the first line and a second line, where the first capacitor is configured to store a charge representing one or more bits. Additionally, each latch unit may include a second capacitor coupled with the first line and a third line, where the second capacitor is configured to amplify a voltage at the first line based on the charge stored in the first capacitor.

System and method for reading and writing memory management data through a non-volatile cell based register

Embodiments of the disclosure are drawn to apparatuses and methods for a sequence of refreshing memory mats. During a refresh operation, wordlines of the memory may be refreshed in a sequence. Groups of wordlines may be organized into memory mats. In order to prevent noise, each time a wordline in a memory mat is refreshed, the next wordline to be refreshed may be in a mat which is not physically adjacent to the mat containing the previously refreshed wordline.

Apparatuses and methods for memory mat refresh sequencing

Methods, systems, and devices for reading and writing memory management data using a non-volatile cell based register are described. A memory device may include a set of latch units addressable via a set of row lines and a set of column lines. Each latch unit may include a sense amplifier coupled with a first line and a first non-volatile capacitor coupled with the first line and a second line, where the first capacitor is configured to store a charge representing one or more bits. Additionally, each latch unit may include a second capacitor coupled with the first line and a third line, where the second capacitor is configured to amplify a voltage at the first line based on the charge stored in the first capacitor.

System and method for reading and writing memory management data using a non-volatile cell based register

Apparatuses and methods for controlling driving signals are disclosed herein. Word drivers may be included in a memory device for driving hierarchical structured main word lines and subword lines. The subword lines may be driven by subword drivers that are activated by main word drivers and word drivers. In driving the word lines, driving signals are driven between an active state having an active voltage and an inactive state having an inactive voltage. The active voltage may be a voltage of a power supply and the inactive voltage may be an intermediate voltage between the active voltage and a reference voltage, such as ground. Driving the driving signals in such a manner may reduce current consumption of the memory device in some operations, for example, such as refresh operations.

Apparatuses and methods for controlling driving signals in semiconductor devices

Apparatuses and methods for controlling driving signals in semiconductor devices including word and subword driver circuits

Apparatuses and methods for maintaining an active state of a word driver signal are described. The word driver may be included in a memory device including a hierarchical structured main word lines and subword lines. The subword lines may be driven by subword drivers that are activated by main word drivers and word drivers. During an operation such as a refresh operation, a driving signal provided by a word driver to a subword driver may be held in an active state while the driving signal provided by a main word driver to the subword driver transitions between active and inactive states. In some examples, the word driver may include a latch for latching an activation signal at an initiation of a refresh operation to maintain a state of the driving signal.

There are provided a vacuum thermal insulating material that is excellent in terms of a handling property, a thermal insulating property, creep resistance, and productivity; and a thermal insulating box including the vacuum thermal insulating material. A core material was enclosed and sealed in a wrapping material with a gas barrier property. The core material of the vacuum thermal insulating material in which the interior of the wrapping material is in a decompression state, is constituted by one organic fibrous assembly having continuous organic fibers formed sheet-shaped or a stack of the organic fibrous assemblies.

Vacuum thermal insulating material and thermal insulating box including the same

In a vacuum thermal insulating material having a core material enclosed in a gas barrier container whose inside is made to be a decompressed state, the core material has a lamination structure in which a plurality of sheet-shaped long fiber organic fibrous assemblies are continuously wound up from an inner periphery to an outer periphery. Then, a plurality of sheet-shaped organic fibrous assemblies are arranged in parallel and sheet-shaped multiple organic fibrous assemblies having joint sections are formed. The joint sections are made not to overlap with the upper and lower of joint sections.

Vacuum thermal insulating material and method of manufacturing the same, and thermal insulating box having the vacuum thermal insulating material

A semiconductor memory device includes a memory cell array, a plurality of data input/output terminals, a plurality of signal paths for writing data supplied to the data input/output terminals to the memory cell array in parallel, a plurality of latch circuits temporarily holding the data on the signal paths, respectively, and a selector selectively supplying the data to the latch circuits from a test data terminal during a test operation. The data can be thereby supplied from the test data terminal to the latch circuits in parallel during the test operation. The number of terminals used at an operation test can be, therefore, greatly decreased.

Semiconductor memory device

When an image is displayed on a display device on the basis of image data, a blank region is formed around the image. A background color is displayed on the blank region. The background color to be displayed on the blank region is set so that its color temperature nearly matches that of a white paper sheet placed under desired illumination light. In this manner, the color tone of a preview image can be adjusted to match that of the original image with high precision.

Print preview and setting background color in accordance with a gamma value, color temperature and illumination types

An image processing apparatus including an area setting unit for setting an area in an image, an image processing setting unit for setting a desired image processing to each area set by the area setting unit, a calculation unit for calculating an outer frame in accordance with the set area, and a designating unit for a user to designate a color of the outer frame, wherein the image is synthesized with the set outer frame having the designated color, and the synthesized image is displayed.

Image processing apparatus and method

An image processor matches a hue of an output image with a hue of a preview image. The image processor generates preview image data to confirm on a display, an output color image generated by an image forming unit. The image processor incudes an input unit which inputs from the image forming unit density data representative of the output color image, the density data depending on the output characteristics of the image forming unit. A conversion unit converts the input density data into luminance data in a predetermined color space, and a color correction unit corrects color of the luminance data in accordance with the display characteristics and observation conditions of the display. The preview image data is generated dependent on the type of display and color temperature of the display.

Growing community of inventors

Nerima, Japan

Nobuo Yamamoto