Hitachi, Ltd.

Nobuo Yagi

Akihiro Umezawa

Kazuki Sato

Hiroshi Kakita

Koichiroh Kato

Dzikowski Jens Uwe

In an information processing system, plural information processing devices are mutually connected by an SMP connection mechanism. Each of the information processing devices includes a control device (FPGA) having a synchronous register that shows the state of a control signal of the information processing device and an internode communication access control unit that transmits first synchronous packets with the content of the synchronous register reflected to the other information processing devices at predetermined time intervals, receives second synchronous packets from the other information processing devices, and reflects the content of the received second synchronous packets on the synchronous register.

System and method for synchronously controlling LED on multiple control modules based on a register synchronized with synchronous packets

A system having an SMP connection made among each information processing apparatus in units of a module including a CPU, a main memory, an HDD and the like, allows use of the HDDs distributed in the system as a single disk. The SMP connection is made among information processing apparatuses each including one or more CPUs, a main memory, one or more storage devices, and a storage device controller that controls the storage device. The storage device controller in a certain information processing apparatus controls the storage device in the information processing apparatus and the storage device in another information processing apparatus. Each information processing apparatus includes a storage device switch for exclusively switching which of the storage device controller in the information processing apparatus and the storage device controller in another information processing apparatus is connected to the storage device in the information processing apparatus.

Information processing and control system for inter processing apparatus control of storage devices

A root port connection functioning as a PCI express bridge, and having a PCI express path constituting a PCI express tree having a PCI express device or switch; when detecting a failure on a PCI express path, a PCI express device or switch transmits a failure signal; the root port transmits an SMI responsive to the failure signal; the CPU executes the BIOS responsive to the SMI; the BIOS collects a log of the PCI express path where failure is detected, analyzes the collected log to judge failure type, and upon a fatal failure on the PCI express path, resets the PCI express tree downstream of the root port that received the failure signal, and upon a non-fatal failure on the PCI express path, resets the PCI express device in which the failure occurred; and the CPU closes the reset PCI express device by executing the device driver.

Arrangements detecting reset PCI express bus in PCI express path, and disabling use of PCI express device

A computer system including a plurality of PCIe paths is configured such that a failed PCIe path only is disabled, thereby preventing the computer system from system resetting. The computer comprises a root port for detecting a failure on a PCIe path, and then for issuing a SMI (System Maintenance Interrupt) to a CPU; and the CPU for, on the receipt of the SMI, executing BIOS to issue, through the root port, a PCIe reset to the PCIe path on which the failure has occurred.

An information processing apparatus includes a data ownership table which is a list of processor numbers having data on each of lines in a level 2 cache. When data at an address pointed by a store instruction exists in the level 2 cache, the apparatus references the table to selectively issue an invalidation request only to a processor in which data at the address exists, but does not issue the request to a processor in which the data does not exist. The path busy ratio can be reduced and the data coherency among processors and a system controller can be maintained with a small amount of logics. When a system controller is divided into a plurality of interleaves operating independently of one another and respectively issuing an invalidation request, the requests issued from the interleaves are put into a queue, and requests having different destination processor numbers are simultaneously issued.

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Tokyo, Japan

Nobuo Yagi