Kabushiki Kaisha Toshiba

Nobuo Watanabe

Shigeo Ohshima

Haruki Toda

Katsumi Abe

Kazuaki Kawaguchi

Yoshinori Ogawa

Koichi Magome

In the package, a semiconductor chip is accommodated. This semiconductor chip has n pads (n is a natural number). The package has n pins connected to n pads.

Semiconductor memory device

A synchronous type semiconductor device which inputs/outputs data with respect to a host includes a memory circuit, command decoder and CAS latency setting circuit. The command decoder decodes a command control signal input from the host in synchronism with a clock input from the host and outputs the decoded command to the memory circuit. The command includes a read command and mode register set command. The CAS latency setting circuit sets CAS latency in a read cycle based on a predetermined command output from the command decoder and a function control signal input from the host. The predetermined command is a command other than the mode register set command.

Synchronous type semiconductor memory device

A semiconductor memory device comprises first and second pins, a controller, a first command decoder and a lower-side command decoder. The controller is supplied with a signal indicating that a read command is input and a signal indicating that a write command is input based on the signal input to the first pin. The first command decoder is controlled by an output signal of the controller, defines the readout/write operation by use of the first command, fetches an upper-side decode address of a memory cell array via the second pin and decodes the first command. A lower-side command decoder is controlled by an output signal of the controller, fetches a lower-side decode address of the memory cell array via the control pin in response to the second command, decodes the lower-side command, and outputs a lower address latch command, mode register set command and auto-refresh command.

Fast cycle RAM and data readout method therefor

A row access command and column access command are supplied as one packet to an FCRAM in two successive clock cycles in order to shorten random access time and random cycle time. At this time, definition of the read/write operation is made by use of a first command and a decode address of a memory cell array is fetched in response to the first command. When the decode address of the memory cell array is fetched in response to the first command, command control pins of the conventional SDR/DDR-SDRAM are used as address pins.

A multiport field memory includes cell arrays, bit line pairs, gate transmission circuits connecting to the bit line pairs, ports, and a data cross-transmission circuit. The data cross-transmission circuit has first and second transfer gate circuit pairs (each pair connected in series and each pair connected to each bit line pair). The ports, each includes a register for temporarily storing data and for transferring the data from or to the memory cell through the bit line pairs. Each port is connected to each bit line pair through each first and second transfer gate circuit pair. The data cross-transmission control circuit has the first and second transfer gate control circuit pairs to transfer first and second gate drive control signals in order to connect the bit line pair to the registers. The first transfer gate circuit in one pair of the first and second transfer gate circuit pairs is connected to the second transfer gate circuit in the same pair or another pair of the first and second transfer gate circuit pairs in order to transfer the data through a desired port under the control of the cross-transmission control circuit.

Multiport field memory

A semiconductor memory device having: a memory cell array with random accessible memory cells disposed in a matrix form, the memory cell array including first memory cell arrays and second memory cell arrays alternately disposed in a column direction, and the first and second memory cell arrays being divided in accordance with a column address; a data register unit for storing one row data of the memory cell array, the data register unit being serially accessed by an external circuit, the data register unit having first data registers and second data registers alternately disposed in the column direction; and a data transfer gate unit including a plurality of data transfer gates for controlling data transfer between the memory cell array and the data register unit, each of the plurality of data transfer gates including a gate for connecting each of the first memory cell array to each of the first data registers, and a gate for connecting each of the second memory array to each of the second data registers, and further including a gate for connecting each of the first memory cell array to each of the second data registers, and a gate for connecting each of the second memory cell arrays to each of the first data registers.

Semiconductor memory device for continuously accessing a memory cell

Multiport semiconductor memory device having RAM blocks and SAM blocks

An address decoder comprising a match signal generating circuit responsive to an inputted address signal and an address mask signal to mask any given bits of the inputted address signal, and an address selection signal generating circuit responsive to signals outputted from the match signal generating circuit, for generating a selection signal of a plurality of addresses which have corresponding bit values except for the masked bits. The address decoder can be used as a row address decoder or column address decoder of the semiconductor memory device for selecting a plurality of addresses simultaneously.

Address decoder which variably selects multiple rows and/or columns and

A plurality of RAM blocks constituting a first RAM section and a second RAM section, respectively are arranged alternately in such a way that the inversion bit lines and the non-inversion bit lines of these RAM blocks are changed alternately block by block and further the two adjacent bit lines of the two adjacent RAM blocks are connected in common as a data line of the SAM blocks. By controlling data transfer control gates for switching on-off conditions of four bit lines of the two adjacent RAM blocks, it is possible to realize a cross transfer such that data can be transferred not only from the RAM blocks of the first RAM section and the second RAM section to the first SAM section and the second SAM section disposed as to correspond to the RAM sections, respectively, but also from the RAM blocks of the first RAM section to the SAM blocks of the adjacent second SAM section and additionally from the RAM blocks of the second RAM section to the RAM blocks of the adjacent first SAM section. Therefore, it is possible to continuously read and write data from and to the same RAM block, in addition to the alternate data read and write operation between the RAM blocks.

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Yokohama, Japan

Nobuo Watanabe