Sony Corporation

Nobuo Ueki

Masuyoshi Kurokawa

Yoichi Yagasaki

Makoto Aoki

Kazuhiko Nishibori

Shinichiro Miyazaki

Akira Shirahama

Ikuo Someya

Hiroyuki Kojima

Takefumi Nagumo

Makoto Kondo

Koji Aoyama

Toshinori Ihara

Takaya Hoshino

Toshio Sarugaku

Yukihiko Mogi

Aya Takechi

Takuya Kitamura

Takashi Kojima

Yoshitaka Morigami

Seiji Kimura

Akira Shimizu

Hironari Sakurai

Shuo Lu

Takeshi Ohno

Hironori Mori

Yuki Tokizaki

The present disclosure relates to image processing apparatus and method intended to be capable of suppressing deterioration in image quality. [Solution] A predicated image is generated using inter-prediction and constrained intra-prediction, the inter-prediction using as a reference image an image of a past frame processed before a current frame, the constrained intra-prediction using no neighboring pixels subjected to inter-prediction, the image of the past frame being encoded, stored in a frame memory, read from the frame memory, and then decoded. The present disclosure is applicable to, in one example, an image processing apparatus, an image coding apparatus, or the like.

Image processing apparatus and method

The present disclosure relates to an image processing device and method that can suppress deterioration of the picture quality by encoding. The image processing device includes a decoding unit configured to decode encoded data obtained by lossy encoding an image of a frame encoded already which is used as a reference image in encoding of an image of a current frame and perform rounding of a decoded image obtained by the decoding with a rounding value whose value is changed over in a time direction of the image. The present disclosure can be applied, for example, to an image processing device, an image encoding device or the like.

Image processing device and method

In order to improve imaging performance, an imaging apparatus is provided to include an image capturing unit configured to detect incident light and generate a raw image data, a compression unit configured to compress the raw image data to generate a coded data having a data amount smaller than that of the raw image data, and an output unit configured to output the coded data to a processing unit for processing the coded data. Furthermore, the image capturing unit, the compression unit, and the output unit are configured to be within a same semiconductor package.

Image pickup element, imaging device, and imaging method

Provided is an image processing apparatus including: an encoder configured to scalably encode image data; a write unit configured to cause storage via a predetermined bus to store encoded data that is the image data scalably encoded by the encoder; a read unit configured to read a desired layer of the encoded data from the storage via the bus; and a decoder configured to scalably decode the encoded data read from the storage by the read unit.

Image processing apparatus and image processing method, image encoding apparatus and image encoding method, and image decoding apparatus and image decoding method

Provided is an image processing device including a congruence degree detecting unit which detects a degree of congruence of each of multiple scenes with respect to an input image made of a two-dimensional image, a depth image generating unit which generates, with respect to the input image, depth images each obtained by a technique corresponding to each of the scenes, a blending unit which blends the depth images, which are generated by the depth image generating unit and each generated by a technique corresponding to each of the scenes, at a blending ratio based on the degree of congruence of each of the scenes, to generate a blended depth image, and a three-dimensional image generating unit which generates a three-dimensional image, which can be viewed three-dimensionally, made of a left-eye image and a right-eye image generated by shifting each pixel of the input image using the blended depth image.

Image processing device, image processing method, and image processing program

An image display apparatus that detects a picture defect and shifts an image region to eliminate the picture defect. The image display apparatus includes a memory unit that temporarily stores an input image signal, a memory control unit that controls a readout start address for the memory unit, a display unit to which the image signal read out of the memory unit is supplied, a detection unit that detects an aspect ratio of the input image signal, and an address control signal generation unit which receives an output from detection unit and generates a readout start address control signal for the memory unit.

Image display apparatus

The present invention provides an image signal processing apparatus and a method thereof in which each of the fields forming the unit-frame is specified, with respect to the inputted image signal, based on a difference value calculated in signal level between a detected pixel in a current field and a detected pixel at the same position in a field which comes one frame behind the current field, a motion vector for a field which comes two frames behind the current field is detected, with respect to the detected pixel in the current field, the detected pixel is shifted, with respect to the specified first field, in a direction opposite to the motion vector within the range of the detected motion vector, the detected pixel is shifted, with respect to the specified fourth field, in a direction along the motion vector, and the detected pixels is shifted, with respect to the specified second and third fields, so as to make the pixels gradually closer to the pixel position shifted with respect to the fourth field, in the consecutive order of the fields from the first field, in the direction along the motion vector or in the direction opposite to the motion vector.

Image signal processing apparatus and processing method

There is provided an image display apparatus which automatically detects a picture defect and shifts an image region to eliminate the picture defect. The image display apparatus includes a memory unit for temporarily storing an input image signal, a memory control unit for controlling a readout start address for the memory unit, a display unit to which the image signal read out of the memory unit is supplied, a detection unit of an aspect ratio of the input image signal, and an address control signal generation unit to which an aspect ratio detection output is supplied from the detection unit and which generates a readout start address control signal for the memory unit from the input image signal. When the input image signal having an aspect ratio different from an aspect ratio of image screen display of the display unit is supplied, a readout start address is controlled on the basis of the address control signal generated by the address control signal generation unit. By this, an image region is automatically shifted and a picture defect is prevented without changing the aspect ratio of the input image signal when an object is a human figure.

An image signal processing apparatus according to the present invention receives an image signal inputted thereto that is generated by subjecting a telecine-converted image to double speed conversion, in which signal one film frame is formed by four fields, identifies a first field on the basis of a difference value calculated between pixel signal levels, and shifts the position of a detected pixel in a vector direction of a motion vector such that an amount of shift is progressively increased as transition is made from the identified first field to the subsequent fields.

Image signal processing apparatus and method

A signal processing apparatus and method for up or down conversion of an interlace signal with a high degree of accuracy. The frequency of a write system clock supplied from a PLL circuit is divided by N by a dividing circuit and then multiplied by M by a multiplying circuit to produce a readout system clock. An interpolation circuit writes a video signal into a frame memory in synchronism with the write system clock from the PLL circuit, and reads out the video signal in synchronism with the readout system clock from the multiplying circuit.

Video signal conversion processing apparatus and method

This invention relates to a video signal converter, a conversion method of video signal, respectively suitable to be applied when a video signal according to National Television System Committee (NTSC) is illustratively converted to a video signal corresponding to an extended graphics array (XGA), an image display unit using the converter and conversion method, and a television receiver. A signal in each field of a video signal S according to NTSC in which the number of lines is 252.5 (effective line number is 240) is converted to a signal in each frame of a video signal S corresponding to XGA in which the number of lines is 840 (effective line number is 768). A video signal converter is composed of an image adaptive double-speed conversion circuit for converting a video signal S to a video signal S according to an interlaced scanning method in which the number of lines is doubled and an interpolation circuit for converting the video signal S to a video signal S . A video signal S acquired by image adaptive conversion processing is a video signal of high image quality. A video signal S acquired by interpolation processing based upon the video signal S is a video signal of high image quality free of the deterioration of the quality of an image, compared with a video signal S acquired only by interpolation processing based upon a video signal S .

Video signal converter, conversion method of video signal, image display unit using them and television receiver

An interpolation interval V,obtained by the picture sizes of the original picture and the converted picture is cumulated by an adder. In the odd field, a selector selects &lsqb;0.5&rsqb; as an offset corresponding to an odd/even field determination signal. In the even field, the selector selects &lsqb;0&rsqb; as an offset corresponding to the odd/even field determination signal. In a vertical blanking interval, the offset is selected as an output. Thus, in the odd field, the offset value &lsqb;0.5&rsqb; is added to the cumulated value of V,. Thereafter, V,is cumulated again. Corresponding to the cumulated value, a line read address n and linear interpolating coefficients q,and q,are obtained. When V,is cumulated, offsets corresponding to the scanning start points in the odd field and the even field are added. Thus, the interlace accuracy is kept.

Picture processing apparatus and processing method

When an image size is changed by using a linear interpolating process, a picture quality is improved so as not to overlap the position of an original signal and the position of an interpolation signal. An interpolation interval Vdp which is derived from an original image and an image size after the conversion is stored into a register of an input side and is accumulated and added by an adder from a register of an output side through a selector. A predetermined calculation is performed and an offset value q.sub.0 is obtained in a circuit. The value q.sub.0 is selected by the selector and the register of the output side is initialized for a vertical blanking period. Thus, a value (.delta.+nVdp) in which the value q.sub.0 was added to the accumulation value of Vdp is derived. On the basis of the value (.delta.+nVdp), a read address (n) of the original image and linear interpolation coefficients q.sub.n1 and q.sub.n2 are obtained. A similar process is also executed for the horizonal direction and an address (m) and coefficients p.sub.n1 and p.sub.n2 are obtained. A proper offset value is added to the interpolating position and the picture quality can be improved without overlapping the original signal and the interpolating position.

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Tokyo, Japan

Nobuo Ueki