Fujitsu Corporation

Nobuo Uchida

Yuji Oinaga

Shoji Nakatani

Mikio Itoh

Yasuhiro Kuroda

Kenji Korekata

To provide a system clock distributing apparatus and a system clock distributing method for reducing a skew of a system clock and a synchronizing signal at low cost. The system clock distributing apparatus for matching the timing of data by using the synchronizing signal includes an oscillatorthat generates a periodical synchronizing signal and a PLLa memory that stores the data, at least one CPUthat conducts a computing process using the data stored in the memory, at least one MACthat controls an access from the CPUto the memory, and at least one NBthat generates the system clock having a frequency that is an integral multiple of the synchronizing signal, and controls the CPUand the MACbased on the operation by the system clock.

System clock distributing apparatus and system clock distributing method

A data processing system including a small throughput access source and a large throughput access source therein for accessing a main storage unit in a consecutive block access mode. The system further includes a detecting unit and a selecting unit. The detecting unit detects an access conflict expected to occur at the same address of the main storage unit. The selecting unit responds to the detection by the detecting unit and momentarily stops the access by the small throughput access source to give priority to the large throughput access source for accessing the conflicting address of the main storage unit.

Data processing system including different throughput access sources

A multiprocessor control system which has at least one main storage unit, a plurality of main storage control units, a plurality of processing units, and a control bus. Each processing unit is connected to the main storage unit through one of the main storage control units. When each processing unit transmits a request for access to at least one main storage unit, the processing units transmit the request to the main storage control units to which each processing unit is connected, and simultaneously, to all of the other main storage control units, through the control bus. All of the main storage control units process the request from the processing unit, synchronously, and execute a busy check control or the like. Data transmitted between each processing unit and an arbitrary one of the main storage units is transmitted only through the main storage control unit to which the processing unit is connected. By using this system, if units needing a high throughput are applied, the system can be controlled in a comparatively simple manner.

Multiprocessor control system

An access priority control system for a main storage for a computer, for controlling a signal transmission to the main storage upon receiving a plurality of storage access requests from at least one processor related to the main storage. The system includes a first access request port unit for holding at least temporarily a segment address of the storage access requests from the processor; a first control unit responsive to the output of the first access request port unit for checking bus conflict conditions and prohibition conditions for a destination storage segment determined by the address of the storage access request; a second access request port unit responsive to the output of the first control unit for holding at least temporarily an intra-segment address of the storage access request; and a second control unit responsive to the output of the second access request port unit for checking logical storage busy conditions in the storage segments.

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Tokyo, Japan

Nobuo Uchida