Renesas Electronics Corporation

Renesas Technology Corp.

Nobuo Tsuboi

Motoshige Igarashi

Yoshiki Yamamoto

Masakazu Okada

Hiroyuki Momono

To improve a reliability of a semiconductor device, a memory cell array is formed in a product region of an SOI substrate, and a test cell array is formed in a scribe region of the SOI substrate. A plurality of regions is formed in each of the memory cell array and the test cell array. The plurality of regions formed in the test cell array is the same configuration as the plurality of regions formed in the memory cell array. A plurality of plugs is formed in the plurality of regions, respectively. Also, it can determine whether or not a leak path is occurred in the memory cell array, by inspecting whether or not a conduction between the plurality of plugs is confirmed.

Method of manufacturing semiconductor device

There is provided with the following semiconductor device to improve its reliability. In a SOI substrate including a semiconductor substrate, an insulating layer, and a semiconductor layer, a diffusion region is formed in the semiconductor layer and a plug electrically connected to the diffusion region is formed on the diffusion region. An element isolation portion is formed within the semiconductor substrate and a trench is formed in the element isolation portion. The lowest part of the bottom of the trench is lower than the surface of the semiconductor substrate and a sidewall spacer is formed in the side portion of the trench to cover the side surface of the insulating layer. As the result, even when the plug is formed in a deviated position, a disadvantage of conducting the semiconductor layer with the semiconductor substrate can be suppressed.

Semiconductor device and method of manufacturing the same

Reliability of a semiconductor device is improved. A p-type MISFET of a thin film SOI type is formed in an SOI substrate including a semiconductor substrate, an insulating layer on the semiconductor substrate, and a semiconductor layer on the insulating layer, and n-type semiconductor regions which are source and drain region of the p-type MISFET are formed in the semiconductor layer and an epitaxial layer on the semiconductor layer. A semiconductor layer is formed via the insulating layer below the p-type MISFET formed in the n-type well region of the semiconductor substrate. In an n-type tap region which is a power supply region of the n-type well region, a silicide layer is formed on a main surface of the n-type well region without interposing the epitaxial layer therebetween.

Semiconductor device

A semiconductor device can be reduced in size. The semiconductor device has a first conductivity type p type well layer extending in the X direction of the main surface of a semiconductor substrate; a reference potential wire coupled with the p type well layer, and extending in the X direction; first and second active regions arranged on the opposite sides of the reference potential wire in the Y direction; and a gate electrode layer extending in the Y direction in such a manner as to cross with the first and second active regions . Then, the gate electrode layer has a first gate electrode of a second conductivity type at the crossing part with the first active region, a second gate electrode of the second conductivity type at the crossing part with the second active region, and a non-doped electrode between the first gate electrode and the second gate electrode.

A semiconductor device can be reduced in size. The semiconductor device has a first conductivity type p type well layer extending in the X direction of the main surface of a semiconductor substrate; a reference potential wire coupled with the p type well layer, and extending in the X direction; first and second active regions arranged on the opposite sides of the reference potential wire in the Y direction; and a gate electrode layer extending in the Y direction in such a manner as to cross with the first and second active regions. Then, the gate electrode layer has a first gate electrode of a second conductivity type at the crossing part with the first active region, a second gate electrode of the second conductivity type at the crossing part with the second active region, and a non-doped electrode between the first gate electrode and the second gate electrode.

A solid-state imaging device includes pixels respectively having photoelectric conversion units and arranged in matrix in basic pattern units, and an optical member arranged on the incidence side of incident light than the pixels and having constituent elements respectively corresponding to the pixels. The pixels include first, second and third wavelength range light pixels. Each basic pattern is comprised of a combined arrangement pattern of the wavelength range light pixels. Misregistration constituent elements with the occurrence of misregistration exist in the constituent elements. The misregistration increases toward the misregistration constituent elements separated from a center position of a pixel array of the pixels. The misregistration of the misregistration constituent element for the first wavelength range light pixel and that of the misregistration constituent element for the third wavelength range light pixel are smaller and larger than that of the misregistration constituent element for the second wavelength range light pixel, respectively.

Solid-state imaging device, layout data generating device and layout data generating method

A semiconductor device in which wirings are formed adequately and electrical couplings are made properly in an SRAM memory cell. In the SRAM memory cell of the semiconductor device, a via to be electrically coupled to a third wiring as a word line is directly coupled to a contact plug electrically coupled to the gate wiring part of an access transistor. Also, another via to be electrically coupled to the third wiring as the word line is directly coupled to a contact plug electrically coupled to the gate wiring part of another access transistor.

A semiconductor device which is designed based on RDR, suppresses the occurrence of a trouble at the boundary between an active region and a power wire and therearound and is small in size and highly integrated. The semiconductor device includes a first conductive impurity region for functional elements which is formed over the main surface of a semiconductor substrate and a second conductive impurity region for power potential to which power potential is applied in at least one standard cell. It also includes insulating layers which are formed over the main surface of the semiconductor substrate and have throughholes reaching the main surface of the semiconductor substrate, and a conductive layer for contact formed in the throughholes of the insulating layers. The impurity region for functional elements and the impurity region for power potential are electrically coupled to each other through the conductive layer for contact which is formed astride the impurity region for functional elements and the impurity region for power potential.

A structure is adopted for a layout of an SRAM cell which provides a local wiringbetween a gateand gateand connects an active regionand an active region. This eliminates the necessity for providing a contact between the gateand the gate. Therefore, it is possible to reduce the size of a memory cell region C in a short side direction. Furthermore, a structure whereby a left end of a gateis retreated from the gateand a local wiringwhich connects the active regionand gatedisposed in a diagonal direction is adopted. This allows the gateto be shifted toward the center of the memory cell region C.

Growing community of inventors

Tokyo, Japan

Nobuo Tsuboi