Hitachi, Ltd.

Nobuo Tomita

Hiroshi Watanabe

Masashi Suenaga

Masayuki Tanji

A high-speed information processing in the information processing unit having a multiplexed bus is provided. A unit having a bus grant is stored in the next lowest priority unit memory circuits, and in the next bus arbitration cycle, bus arbitration is carried out by setting the lowest priority to the unit stored in the next lowest priority unit memory circuits. When a fault occurs in one of a plurality of buses and then the faulty bus recovered a normal operation status, the bus status supervising circuits output has fault recovery detecting signals and match the memory contents of the next lowest priority unit memory circuits together. With the above arrangement, an average bus waiting time can be minimized and the bus waiting time can be limited.

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Hitachi, Japan

Nobuo Tomita