Hitachi, Ltd.

Renesas Technology Corp.

Hitachi Ulsi Systems Co., Ltd.

Nobuo Shibasaki

Toshio Tanaka

Hiromasa Takahashi

Naoki Yashiki

Hiroyuki Kida

Satoshi Yamato

Seiji Kamada

Tsutomu Ishii

Hiroyuki Matsuura

Mitsuo Hagiwara

Masanobu Kawamura

Toshiyuki Tojo

Mitsuo Yotsutani

Takeshi Ohkubo

Hiroyuki Sakai

Kenjiro Yasunari

Yoshiharu Nagayama

A microcomputer which is an integrated circuit including an electrically erasable and programmable nonvolatile semiconductor memory and a central processing unit is used for control of a disk drive. The nonvolatile semiconductor memory holds an application program such as a recorded information reproducing control program in an application program area, and holds a reboot program used for updating the application program in a reboot program area. The central processing unit executes the reboot program to rewrite the application program in whole or part, in response to a rewrite command for the application program which is supplied from the outside.

Disk drive and computer

A microcomputer ( ) which is an integrated circuit including an electrically erasable and programmable nonvolatile semiconductor memory ( ) and a central processing unit ( ) is used for control of a disk drive ( ). The nonvolatile semiconductor memory holds an application program such as a recorded information reproducing control program in an application program area ( ), and holds a reboot program used for updating the application program in a reboot program area ( ). The central processing unit executes the reboot program to rewrite the application program in whole or part, in response to a rewrite command for the application program which is supplied from the outside.

Disk drive computer with programmable nonvolatile memory capable of rewriting a control program of the disk drive

A variable wave forming circuit is provided which produces signals of various waveforms (e.g., sine, triangular or trapezoidal waves) and various frequencies. A random access memory (memory means) 121 to store wave formation information on waveform is provided. According to the wave formation information stored in the memory means, the updating or keeping of a digital value in an increment/decrement circuit 123 is controlled and the digital value is digital/analog-converted by a digital/analog (D/A) conversion circuit 124, which is controlled by a digital value control means that includes the increment/decrement circuit 123. By writing appropriate wave formation information into the memory means, it is possible to produce signals of desired waveforms.

Method of forming a signal wave from first and second waveform data

Finely adjustable signal wave forming circuit including complementary

A microprocessor having a plurality of memories comprises an address selection means which supplies selectively, to the memories, the address signal generated by the address generation means provided in the microprocessor and the test address signal supplied from the external circuit. Thereby, the address of memories can be accessed directly from the external circuit for the test of memories. Moreover, the microprocessor is provided with the test bus through which the signal transmitted between the function blocks in the microprocessor is input or output from or to the external circuit. Accordingly, the function block can be tested easily.

Semiconductor integrated circuit device

A memory address signal for a display memory is generated from a memory address generating circuit. The memory address generating circuit has an offset register and a memory address counter in addition to a memory address register. The offset register stores an offset value corresponding to a difference between a width of the display memory and a width of a display picture in a scanning direction. The memory address counter counts up a character clock in order to deliver the memory address signal after loading a start address of each horizontal scanning line of the display picture. At the end of each horizontal scanning line, an adder adds the offset value to the memory address signal. The addition thereof is loaded into the address register as the start address of the next horizontal scanning line.

Apparatus for generating memory address of a display memory

Growing community of inventors

Kodaira, Japan

Nobuo Shibasaki