Other

Nec Corporation

Nobuo Nagano

Kazuhiko Onda

Taku Sato

Junichi Somei

Seiji Ichikawa

Fumie Ogihara

Tatsuo Tokue

A matrix switch device comprises a semiconductor integrated circuit chip comprising a 2&times;2 matrix switch having two input terminals and two output terminals and an SPDT switch at a stage subsequent to the 2&times;2 matrix switch, the SPDT switch having two input terminals and one output terminal, wherein electrical connection is performed between one of the output terminals of the 2&times;2 matrix switch and one of the input terminals of the SPDT switch, and wherein the two input terminals and the other of said output terminals of the 2&times;2 matrix switch, and the other input terminal and the output terminal of the SPDT switch are led out of the semiconductor integrated circuit chip.

Matrix switch device high in isolation between terminals thereof, small in size, and low in manufacturing cost

A method of producing a semiconductor device of the present invention is applicable to a multilayer wafer for leadless chip carrier packages and breaks it on a package basis. The method begins with a step of forming a generally V-shaped groove in one major surfaces of the wafer in the direction of thickness of the wafer. A weak, cleaving portion is formed in the other major surface of the wafer in alignment with the groove. A cleaving force is exerted on the wafer to thereby form a break in the cleaving portion, so that the wafer is caused to break from the groove toward the cleaving portion in the direction of thickness of the wafer. The cleaving portion may be replaced with a strong, non-cleaving portion, in which case the break is formed in the interface between the non-cleaving portion and the wafer due to a difference in cleaving force.

Method of producing a semiconductor device

Growing community of inventors

Tokyo, Japan

Nobuo Nagano