Hitachi, Ltd.

Nobuo Kotera

Hirotoshi Tanaka

Satoshi Tanaka

Minoru Nagata

Kiichi Yamashita

Taizo Kinoshita

Ushio Kawabe

Yutaka Harada

Atsushi Asano

Tetsu Oi

Nobuo Miyamoto

Yasushi Hatta

Kunio Yamashita

Shoji Shukuri

Yasunari Umemoto

Hiroyuki Tanaka

Takehisa Hayashi

Tomoyuki Watanabe

Kiichi Ueyanagi

Yasuo Wada

Noboru Masuda

Takashi Nishida

Juichi Morikawa

Norikazu Hashimoto

Junji Shigeta

Keiichi Kitamura

Nobutoshi Matsunaga

Muneyasu Nakashima

Yuji Hatano

A semiconductor circuit including first and second FET's for delivering an output signal without being affected by a change in threshold voltage of the FET's is disclosed. According to one practical form of the semiconductor circuit, the drain-source current path of an additional FET whose gate and source are shorted to each other, is connected in parallel to the drain-source current path of the first FET whose gate and drain are shorted to each other, to make the voltage-current characteristic of the second FET agree with that of the parallel combination of the first and additional FET's. According to another practical form of the semiconductor circuit, a voltage dividing circuit is connected in parallel to the drain-source current path of the first FET, and a divided output voltage from the voltage dividing circuit is applied between the gate and source of each of the first and second FET's.

Current mirror circuit employing depletion mode FETs

A field effect transistor formed on a semi-insulator or compound semiconductor substrate comprises a first semiconductor layer forming a source region, a drain region and a channel layer, and a second semiconductor layer having a reverse conduction type to that of the first semiconductor layer. The second semiconductor layer is doped so that it will be totally depleted. Therefore, a portion of the second semiconductor layer adjacent to the substrate will remain conductive. The field effect transistor with this structure prevents the short channel effect and the soft error due to .alpha.-particles. A threshold voltage control arrangement is also provided using the feature of a control electrode coupled to the second semiconductor layer and a feedback arrangement.

Field effect transistor

A logic circuit made up of FET's is disclosed in which an output interface circuit is formed of a source follower circuit including a signal transmitting FET and a constant-current supplying FET, and a ratio of the gate width of the signal transmitting FET to the gate width of the constant-current supplying FET is set so that the high and low levels of the output signal of the logic circuit are independent of the threshold voltage of the FET's.

MESFET circuit with threshold-compensated source-follower output

A wide-band and high-gain differential amplifier adapted to amplifying transmitted optical signals of the GHz band is constituted by GaAs MESFET's. Two MESFET's Q1 and Q2 are differentially connected to each other. Drains of Q1 and Q2 are connected to load resistances R.sub.L and R.sub.L via a source-drain path of other MESFET's Q3 and Q4 whose gates are grounded in AC-wise. Current by-passing means 4, 4 are connected to the sources of other MESFET's Q3, Q4. DC bias currents of the differential pair of MESFET's Q1, Q2 are set to relatively large values to increase the mutual conductance gm of the differential pair of MESFET's Q1, Q2. Despite a large DC bias current, the current by-passing means 4, 4 decrease the DC voltage drops across the load resistances R.sub.L, R.sub.L, and enable the differntial amplifier to operate on a low power source voltage.

Amplifying circuit

This invention relates to a threshold voltage detection circuit for detecting the threshold voltage of field effect transistors (FETs) and to a semiconductor circuit capable of a stable operation irrespective of the fluctuation of the threshold voltage by utilizing this threshold voltage detection circuit. The source-drain path of first FET is connected in series with that of second FET having substantially the same threshold voltage as that of the first FET and the conductances of these first and second FETs are set to a predetermined ratio to generate a voltage drop associated with the threshold voltage in the first FET. This voltage drop can be used for detecting the threshold voltage and for level-shifting. The output of the series connection of the first and second FETs is applied to the gate of a constant current FET having the same threshold voltage as that of the first and second FETs and the drain current of the constant current FET can thus be set irrespective of the fluctuation of the threshold voltage.

Threshold voltage fluctuation compensation circuit for FETS

A constant voltage circuit according to this invention comprises first means attenuating or dividing fluctuating voltage and an amplifying FET, to the gate of which the output attenuated or divided by the first means is applied and whose drain is connected with the fluctuating voltage through load means. The attenuation ratio or division ratio of the first means, the mutual conductance of the amplifying FET and the impedance of the load means are so set that the voltage drop across the load means cancels the fluctuating amount of the fluctuating voltage. Consequently an output voltage, which is maintained substantially constant, is obtained at the drain of the amplifying FET, independently of fluctuations in the fluctuating voltage, and thus a constant voltage circuit can be obtained. A constant current circuit according to this invention utilizes the constant voltage circuit described above. The output voltage of the constant voltage circuit is supplied to the gate of the constant current FET. Consequently a current, which is maintained substantially constant, flows through the drain-source path of this constant current FET and thus a constant current circuit can be obtained.

Semiconductor circuit

A constant current circuit includes a first FET providing an input reference current flow, a second FET providing an output current flow and a non-linear impedance element connected between the drain and the gate of the first FET. By setting a parameter of the non-linear impedance element and a parameter of the first FET to have a specific relationship with each other, the output current can be maintained at a substantially definite value irrespective of relatively large variations of the input reference current.

Constant current circuit

A Josephson logic integrated circuit packaged on a single substrate, wherein a portion for delivering an output out of the integrated circuit is constructed of an A.C.-driven Josephson logic circuit, and a portion for driving the internal part of the integrated circuit is constructed of a D.C.-driven Josephson logic circuit.

Josephson logic integrated circuit

A rectifying circuit includes a superconductive device and a circuit which controls a magnetic field to be applied to the superconductive device in response to the phase of an A.C. signal applied to the superconductive device, the state of the superconductive device being alternately and repeatedly changed-over between a superconductive state and a nonsuperconductive state by the magnetic field so as to rectify the A.C. signal.

Rectifying circuit comprising a superconductive device

A superconducting logic circuit including a first power source terminal connected with a current source; a second power source terminal connected with a current sink; a first superconducting switching device connected between said first power source terminal and ground; a second superconducting switching device connected between said second power source terminal and ground; first and second resistors connected with said first and second power source terminals, respectively; and third and fourth resistors connected with the control terminals of said first and second superconducting switching devices, respectively, wherein the other terminals of said first and second resistors are connected with each other to provide a logic output terminal, and wherein the other terminals of said third and fourth resistors are connected with each other to provide a logic input terminal.

Superconducting logic circuit and superconducting switching device

A superconductive large-scale integrated circuit chip comprises a plurality of pads, a superconductive line which short-circuits respectively adjacent pairs of the pads, and an input buffer circuit. The input buffer circuit includes a Josephson junction which is either in a superconducting state or a finite voltage state in response to a magnetic field established by current that is supplied to the superconductive line by flowing in from one of the two pads and flowing out from the other pad. The input buffer circuit wave-shapes the externally supplied signal into an amplitude-controlled signal, and the latter signal is led by a superconductive line to a circuit within the chip which requires the signal. Even when the external signal current has become abnormally great due to noise, etc., any circuit situated halfway within the chip can be prevented from malfunctioning from the magnetic flux generated by the large current.

Superconductive large-scale integrated circuit chip

A basically cross-shaped semiconductor Hall element comprises a pair of current-supplying electrodes as well as a pair of Hall electrodes. The structure includes trapezoidal semiconductor regions extending from the central magneto-sensitive region in both the current-supplying electrode directions to thereby suppress the element temperature rise due to Joule heating. In addition, the contiguous slant edges of the extended trapezoidal portion form an angle .theta. greater than 90.degree. with lateral edges of the central rectangular magneto-sensitive region to thereby suppress the semiconductor noise dependent on the shape itself.

Hall element

A method for laser zone melting and apparatuses therefor wherein, in a zone melting method for a thin film due to the irradiation of laser beam, the laser beam is vibrated at the frequency of more than 1 Hz in the direction substantially perpendicular to the moving direction of a melting zone and the fluctuation of laser beam output is controlled to less than 1%. The zone-melted thin films manufactured by this method have good electrical properties resulting from less crystal imperfection, less non-stoichiometric excess atoms of the constituents, and less thickness corrugation of the film due to the suppression of temperature fluctuations and its spacial inhomogeneity at the time of zone melting.

Method and apparatus for laser zone melting

A method for producing an InSb thin film element comprising the steps of forming an InSb polycrystalline thin film on a substrate, melting and recrystallizing the InSb polycrystalline thin film at a temperature above the melting point of InSb, and disposing a diffusion source which contains at least one element selected from the group consisting of Cu, Au, Ag, Zn, Na, K, Cd, B, Li, Ca, Fe, Mg, Ba, Al and Pb and then heating the InSb thin film so as to dope it with the desired element or elements in a range in which the total quantity does not exceed a concentration of 1.times.10.sup.18 cm.sup.-3. The InSb thin film element produced by this method has a very little current noise and a high signal-to-noise ratio. Further more, simultaneous doping of the said predetermined element or said elements and sb is more effective to reduce the current noise.

Method for producing an InSb thin film element

A method for producing an InSb thin film element comprising the steps of (i) preparing a substrate at least one surface of which is made of alumina or an inorganic insulating material containing at least 12 mol % of alumina, and forming an InSb thin film of a thickness of at most 0.2 .mu.m on the surface of said substrate, (ii) depositing on said InSb thin film a film which is made of an inorganic insulating material containing at least 12 mol % of alumina, (iii) heating said InSb thin film above the melting point of InSb, and (iv) cooling said InSb thin film and recrystallizing InSb. The InSb thin film element thus produced has the InSb thin film whose thickness is at most 0.2 .mu.m, whose surface is flat and which has good electrical characteristics.

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Kokubunji, Japan

Nobuo Kotera