Sanken Electric Co., Ltd.

Nobuo Kaneko

Ken Sato

Koji Otsuka

Masataka Yanagihara

A compound semiconductor device is comprised of: a compound semiconductor layer including a first active layer and a second active layer forming a hetero junction with the first active layer so as to naturally generate a two-dimensional carrier gas channel in the first active layer along the hetero junction; a first electrode formed on the second active layer; a second electrode in ohmic contact with the first active layer and isolated from the first electrode; and a channel modifier for locally changing a part of the first active layer under the channel modifier into a normally-off state, the channel modifier being formed on the second active layer so as to enclose but be isolated from the first electrode and the second electrode.

Compound semiconductor device and production method thereof

A object is to provide a semiconductor device having normally-off characteristics and capable of easily suppressing field concentration below a side surface of a concave portion. A device includes a nitride-based semiconductor layer having a concave portion formed in a part of one principal surface, a side surface of the concave portion being slanted; a first electrode provided on the principal surface; a second electrode on an opposite side to the first electrode across the concave portion, and provided on the principal surface; an insulating layer formed on both sides of the concave portion in the principal surface; and

Semiconductor device and method for manufacturing the same

An object of the present invention is to reduce on-state resistance and increases reliability in a semiconductor device having an electrode formed in a recessed structure. As illustrated in FIG.B, a first insulating layeris formed. Then, as illustrated in FIG.C, a photolithography process is carried out to form a photoresist pattern. Subsequently, as illustrated in FIG.D, dry etching is applied to the first insulating layer. Then, as illustrated in FIG.E, a laminated semiconductor structure is etched. Next, in this state, wet etching is applied to the first insulating layeras illustrated in FIG.F. Next, in this state, an electrode materialis formed on the entire exposed surface as illustrated in FIG.G. Finally, as illustrated inH, the photoresist patternis removed.

Semiconductor device and its manufacturing method

A semiconductor deviceincludes a substratehaving on a main surface thereof a central area and a peripheral area which surrounds the central area and is exposed, a semiconductor layerwhich is formed on the main surface of the substrate, is made of a material harder than the substrate, is in the shape of a mesa, and has a steep side over the exposed peripheral area, and an insulating filmS provided on a side surface of the semiconductor layer

Semiconductor device having resistance layer formed on side surface of semiconductor layer

A heterojunction field-effect semiconductor device has a main semiconductor region comprising two layers of dissimilar materials such that a two-dimensional electron gas layer is generated along the heterojunction between the two layers. A source and a drain electrode are placed in spaced positions on a major surface of the main semiconductor region and electrically coupled to the 2DEG layer. Between these electrodes, a gate electrode is received in a recess in the major surface of the main semiconductor region via a p-type metal oxide semiconductor film and insulating film, whereby a depletion zone is normally created in the 2DEG layer, making the device normally off. The p-type metal oxide semiconductor film of high hole concentration serves for the normally-off performance of the device with low gate leak current, and the insulating film for further reduction of gate leak current.

Field-effect semiconductor device

A HEMT-type field-effect semiconductor device has a main semiconductor region comprising two layers of dissimilar materials such that a two-dimensional electron gas layer is generated along the heterojunction between the two layers. A source and a drain electrode are placed in spaced positions on a major surface of the main semiconductor region. Between these electrodes, a gate electrode is received in a recess in the major surface of the main semiconductor region via a p-type metal oxide semiconductor film whereby a depletion zone is normally created in the electron gas layer, with a minimum of turn-on resistance and gate leak current.

Semiconductor device and method of manufacturing the same

A substrate system of the kind having a buffer region interposed between a silicon substrate proper and a nitride semiconductor region in order to make up for a difference in linear expansion coefficient therebetween. Electrodes are formed on the nitride semiconductor layer or layers in order to provide HEMTs or MESFETs. The buffer region is a lamination of a multiplicity of buffer layers each comprising a first, a second, and a third buffer sublayer of nitride semiconductors, in that order from the silicon substrate proper toward the nitride semiconductor region. The three sublayers of each buffer layer contain aluminum in varying proportions including zero. The aluminum proportion of the third buffer sublayer is either zero or intermediate that of the first buffer sublayer and that of the second. The low aluminum proportion of the third buffer sublayer serves to prevent two-dimensional electron gas from generating in the buffer region and hence to make this region sufficiently high in resistance to inhibit current leakage from the HEMTs or MESFETs.

Nitride semiconductor substrate and semiconductor element built thereon

A high electron mobility transistor is disclosed which has a double-layered main semiconductor region formed on a silicon substrate via a multilayered buffer region. The multilayered buffer region is in the form of alternations of an aluminum nitride layer and a gallium nitride layer. The main semiconductor region, buffer region, and part of the substrate taper as they extend away from the rest of the substrate, providing slanting side surfaces. An electroconductive antileakage overlay covers these side surfaces via an electrically insulating overlay. Electrically coupled to the silicon substrate via a contact electrode, the antileakage overlay serves for reduction of current leakage along the side surfaces.

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Niiza, Japan

Nobuo Kaneko