Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Socionext Inc.

Matsushita Electric Ind. Co., Ltd.

Nobuo Higaki

Shuichi Takayama

Tetsuya Tanaka

Shinya Miyaji

Taketo Heishi

Kensuke Odani

Tokuzo Kiyohara

Hideshi Nishida

Hajime Ogawa

Masato Suzuki

Toru Morikawa

Kozo Kimura

Hiroshi Kadota

Kunihiko Hayashi

Kazuya Furukawa

Kazushi Kurata

Shigeki Fujii

Nobuki Tominaga

Toshio Sugimura

Kenichi Kawaguchi

Keizo Sumida

Akira Tanaka

Akira Miyoshi

Toshimichi Matsuzaki

Hiroyuki Morishita

Tomonori Kataoka

Seiichi Urushibara

Satoshi Ogura

Kouzou Kimura

Masayuki Kozuka

Kazuhiko Yamauchi

Yasushi Uesaka

Masaitsu Nakajima

Shinji Ozaki

Akihiro Furuta

Kazushi Yamamoto

Yoshito Nishimichi

Masashi Deguchi

Takeshi Furuta

Hideyo Tsuruta

Koichi Horiuchi

Takahiro Kageyama

Tsuneyuki Suzuki

Yuya Shigenobu

Keisuke Kaneko

Syusuke Haruna

Kousuke Yoshioka

Takao Kawakami

Yousuke Kudo

Shuishi Takayama

Motokazu Ozawa

Masaki Minami

A signal-processing apparatus includes an instruction-parallel processor, a first data-parallel processor, a second data-parallel processor, and a motion detection unit, a de-blocking filtering unit and a variable-length coding/decoding unit which are dedicated hardware. With this structure, during signal processing of an image compression and decompression algorithm needing a large amount of processing, the load is distributed between software and hardware, so that the signal-processing apparatus can realize high processing capability and flexibility.

Signal-processing apparatus including a second processor that, after receiving an instruction from a first processor, independantly controls a second data processing unit without further instruction from the first processor

Signal-processing apparatus including a second processor that, after receiving an instruction from a first processor, independantly controls a second data processing unit without further instrcuction from the first processor

A processor executes a plurality of tasks by switching a timeslot and iterating a plurality of timeslots. The processor includes a table in which tasks are defined in correspondence with timeslots. In the table, the number of timeslots to be held in one iteration is defined, for each of the timeslots a total time period during the predetermined number of iterations is designated, and a plurality of tasks are defined in correspondence with at least one of the timeslots. A timeslot is switched every time a predetermined period elapses. One task is selected and executed by referring to the table in correspondence with switching of timeslot.

Processor and program execution method capable of efficient program execution

A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.

A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction 'MCSST Dis decoded, the sum-product result registeroutputs its held value to the path PThe comparatorcompares the magnitude of the held value of the sum-product result registerwith the coded 32-bit integer '0x0000_00FF'. The polarity judging unitjudges whether the eighth bit of the value held by the sum-product result registeris &#x201c;ON'. The multiplexeroutputs one of the maximum value &#x201c;0x0000_00FF&#x201d; generated by the constant generatorthe zero value &#x201c;0x0000_0000&#x201d; generated by the zero generatorand the held value of the sum-product result registerto the data bus

Processor which can favorably execute a rounding process composed of positive conversion and saturated calculation processing

A 32-bit instructionis composed of a 4-bit format field, a 4-bit operation field, and two 12-bit operation fieldsand. The 4-bit operation fieldcan only include (1) an operation code 'cc' that indicates a branch operation which uses a stored value of the implicitly indicated constant registeras the branch address, or (2) a constant 'const'. The content of the 4-bit operation fieldis specified by a format code provided in the format field

Processor for executing highly efficient VLIW

A variable-length code decoding apparatus that decodes a bitstream includes: a storage unit that stores a variable-length code table; a bitstream cutout unit that outputs a bit string of a fixed length; a reference unit that outputs decoded data and a code length with reference to the storage unit; a determination unit that determines whether a bit string of the fixed length is accumulated; a determination unit that determines whether a bit string of a length that is shorter than the fixed length is accumulated; and a selection unit that selects one of the determination results from the determination units. The bitstream cutout unit sets a starting bit based on the selected determination result, and the selection unit switches the selection of the determination results from the determination units.

Variable-length code decoding apparatus and method

A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction 'MCSST D' is decoded, the sum-product result registeroutputs its held value to the path P. The comparatorcompares the magnitude of the held value of the sum-product result registerwith the coded 32-bit integer '0x0000_00FF'. The polarity judging unitjudges whether the eighth bit of the value held by the sum-product result registeris &#x201c;ON&#x201d;. The multiplexeroutputs one of the maximum value &#x201c;0x0000_00FF&#x201d; generated by the constant generator, the zero value &#x201c;0x0000_0000&#x201d; generated by the zero generator, and the held value of the sum-product result registerto the data bus

When a branch instruction is decoded by the instruction decoders, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculatorand the lower 3 bits are sent to the lower PC calculator. The lower PC calculatoradds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PCand sends the result to the lower PCas the updated lower PC. The upper PC calculatoradds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC, and a carry that may be received from the lower PC calculator, and sends the result to the upper PCas the updated upper PC.

Processor for executing instructions in units that are unrelated to the units in which instructions are read, and a compiler, an optimization apparatus, an assembler, a linker, a debugger and a disassembler for such processor

A processor can decode short instructions with a word length equal to one unit field and long instructions with a word length equal to two unit fields. An opcode of each kind of instruction is arranged into the first unit field assigned to the instruction. The number of instructions to be executed by the processor in parallel is s. When the ratio of short to long instructions is s-1:1, the s-1 short instructions are assigned to the first unit field to the s-1unit field in the parallel execution code, and the long instruction is assigned to the sunit field to the (s+k&#x2212;1)unit field in the same parallel execution code.

Instruction converting apparatus using parallel execution code

In order to overcome the problem that conditionally executed instructions are executed as no-operation instructions if their condition is not fulfilled, leading to poor utilization efficiency of the hardware and lowering the effective performance, the processor decodes a number of instructions that is greater than the number of provided computing units and judges their execution conditions with an instruction issue control portion before the execution stage, Instructions for which the condition is false are invalidated, and subsequent valid instructions are assigned so that the computing units (hardware) is used efficiently. A compiler performs scheduling such that the number of instructions whose execution condition is true does not exceed the upper limit of the degree of parallelism of the hardware. The number of instructions arranged in parallel at each cycle may exceed the degree of parallelism of the hardware.

Processor, compiler and compilation method

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Kobe, Japan

Nobuo Higaki