Kabushiki Kaisha Toshiba

Other

Tokyo Electron Limited

Ibiden Company Limited

Ebara Corporation

Tokyo Electron Yamanashi Limited

Nobuo Hayasaka

Katsuya Okumura

Haruo Okano

Hisashi Kaneko

Mie Matsuo

Keiichi Sasaki

Rempei Nakata

Junichi Wada

Hideki Shibata

Takamasa Usui

Masahiko Hasunuma

Hideshi Miyajima

Hiroshi Ikegami

Kyoichi Suguro

Atsuko Sakata

Noriaki Matsunaga

Tomio Katata

Yoshimi Hisatsune

Hiroyuki Yano

Yasutaka Sasaki

Jun-ichi Wada

Yusuke Kohyama

Tetsuo Matsuda

Kiyoshi Takekoshi

Junichi Hagihara

Hirotaka Nishino

Hisatomi Hosaka

Hitoshi Ito

Yoshiyuki Ido

Manabu Kimura

Kunihiko Hatsushika

Koji Sakui

Shinichi Ito

Norio Kimura

Masayuki Hattori

Koji Mishima

Kenji Nakamura

Hiroaki Inoue

Akihiro Kajita

Junji Kunisawa

Manabu Tsujimura

Masako Kodera

Sachiyo Ito

Riichirou Aoki

Tsunetoshi Arikado

Itsuko Sakai

Natsuki Makino

Akira Iio

Yukio Nishiyama

Takashi Yoda

Toshiyuki Morita

Haruki Nojo

Keizo Shimamura

Takahito Nagamatsu

Mitsuko Odagaki

Junsei Tsutsumi

Akemi Satoh

Masao Toyosaki

Ryota Katsumata

Akihiro Kojima

Ichiro Mizushima

Junichi Miyamoto

Naoki Yasuda

Kazuya Nagaseki

Chiaki Takubo

Gaku Minamihaba

Yukiteru Matsui

Shinji Himori

Keiji Horioka

Miyoko Shimada

Yasuhiro Horiike

Makoto Sekine

Tokuhisa Ohiwa

Tsukasa Azuma

Iwao Higashikawa

Tatsuhiko Higashiki

Hideaki Hirabayashi

Yoshikuni Tateyama

Akio Ui

Masayuki Motonari

Nobuyuki Kurashima

Shoji Seta

Takeshi Nishioka

Nobuhide Yamada

Tsuyoshi Haga

Kenro Nakamura

Naruhiko Kaji

Ayako Shimazaki

Hideto Matsuyama

Hidemi Ishiuchi

Yutaka Nakano

Masatoshi Higuchi

Kiyonobu Kubota

Junko Ohuchi

Hideo Ichinose

Syuji Mochizuki

Masaki Hotta

A reliability evaluation test apparatus of this invention includes a wafer storage section which stores a wafer in a state wherein the electrode pads of a number of devices formed on the wafer and the bumps of a contactor are totally in electrical contact with each other. The wafer storage section transmits/receives a test signal to/from a measurement section and has a hermetic and heat insulating structure. The wafer storage section has a pressure mechanism which presses the contactor and a heating mechanism which directly heats the wafer totally in contact with the contactor to a predetermined high temperature. The reliability of an interconnection film and insulating film formed on the semiconductor wafer are evaluated under an accelerated condition.

Reliability evaluation test apparatus, reliability evaluation test system, contactor, and reliability evaluation test method

A multichip semiconductor device is disclosed in which chips are stacked each of which comprises a semiconductor substrate formed on top with circuit components and an interlayer insulating film formed on the top of the semiconductor substrate. At least one of the chips has a connect plug of a metal formed in a through hole that passes through the semiconductor substrate and the interlayer insulating film. The chip with the connect plug is electrically connected with another chip by that connect plug.

Multichip semiconductor device, chip therefor and method of formation thereof

A plating method and apparatus for a substrate fills a metal, e.g., copper, into a fine interconnection pattern formed in a semiconductor substrate. The apparatus has a substrate holding portionhorizontally holding and rotating a substrate with its surface to be plated facing upward. A seal materialcontacts a peripheral edge portion of the surface, sealing the portion in a watertight manner. A cathode electrodepasses an electric current upon contact with the substrate. A cathode portionrotates integrally with the substrate holding portionAn electrode arm portionis above the cathode portionand movable horizontally and vertically and has an anodeface-down. Plating liquid is poured into a space between the surface to be plated and the anodebrought close to the surface to be plated. Thus, plating treatment and treatments incidental thereto can be performed by a single unit.

Method of performing electrolytic treatment on a conductive layer of a substrate

Form a trench in a major surface of a semiconductor substrate, then bury a paste in the trench. The paste contains solids having a conductive substance and a resin, and solvent for dissolving the resin. The solids content of the paste is not less than 60 vol % and a viscosity ratio thereof is not more than 2.

Paste including a mixture of powders, connection plug, burying method, and semiconductor device manufacturing method

A probe pin for testing electric characteristics of a semiconductor device comprises a silicon pin core (), and a conductive film () covering the entire surface, including the bottom face, of the pin core. The bottom face of the probe pin is connected directly to an electrode () positioned in or on a print wiring board. A number of probe pins can be connected to the associated electrodes at a high density, thereby forming a fine-pitch probe card having a superior high-frequency signal characteristic.

Method for fabricating a probe pin for testing electrical characteristics of an apparatus

A gate insulation film is formed on a semiconductor substrate, gate electrodes are formed on the gate insulation film, and source/drain diffusion layers are formed. A silicon nitride films is formed on a side wall of the gate electrodes, a silicon oxide film is formed on the overall surface, and the silicon oxide film is etched back to have the same height as that of the gate electrodes so that the surface is flattened, and then the surface of the gate electrodes are etched by a predetermined thickness to form a first stepped portion from the silicon oxide film, the first stepped portion is filled up by a tungsten film, the surface of the tungsten film is etched by a predetermined thickness so that a second stepped portion is formed, and then the second stepped portion is filled by a silicon nitride films.

Semiconductor device using damascene technique and manufacturing method therefor

A method of manufacturing semiconductor device which comprises the steps of forming an insulating film on an Si substrate provided with a wiring layer, forming a contact hole connected to the wiring layer and a wiring groove in the insulating film, filling the contact hole with an Si film, successively forming an Al film and a Ti film all over the substrate, performing a heat treatment thereby to substitute the Al film for the Ti film, and to allow the Si film to be absorbed by the Ti film, whereby filling the contact hole and wiring groove with the Al film, and removing a Ti/Ti silicide which is consisting of Ti silicide formed through the absorption of the Si film by the Ti film and a superfluous Ti, whereby filling the contact hole with an Al plug and filling the wiring groove with an Al wiring.

Semiconductor device and method for manufacturing the same

After a barrier film is formed on a pad electrode, Ni particles having a diameter of 2 &#x3bc;m or less are selectively deposited on the barrier film, thereby forming a Ni fine particle film. Then, a bump electrode made of a solder ball is provided on the pad electrode through the Ni fine particle film. Thereafter, the bump electrode is melted by a heat treatment to join the Ni fine particle film to the bump electrode. Thus, a bump electrode structure is finished.

Fine particle film forming apparatus and method and semiconductor device and manufacturing method for the same

The present invention provides an integrated circuit, comprising a semiconductor substrate, an active element formed on the side of one main surface of the semiconductor substrate, an insulating region formed on the side of the main surface of the semiconductor substrate by burying an insulating material in a groove having a depth of at least 20 &#x3bc;m, and a passive element formed directly or indirectly on the insulating region. It is desirable for the passive element to be an inductor.

Integrated circuit device and method of manufacturing the same

According to the present invention, there is provided a method of manufacturing a semiconductor device, where a soluble thin film which is soluble in a dissolving liquid is used. According to the method of the present invention, when a soluble thin film is formed between a film to be processed which should be patterned and a mask pattern, it becomes possible to remove the mask pattern by lifting-off. On the other hand, when the thin film is used for a dummy layer for forming an air wiring structure, the dummy layer can be removed without performing ashing using oxygen plasma.

High precision pattern forming method of manufacturing a semiconductor device

Growing community of inventors

Yokosuka, Japan

Nobuo Hayasaka