Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Electric Corporation

Renesas Technology Corp.

Nobuo Fujiwara

Kenji Kawai

Tomonori Okudaira

Takeharu Kuroiwa

Keiichiro Kashihara

Teruo Shibano

Kyusaku Nishioka

Yasuhiro Kagawa

Takahiro Maruyama

Yutaka Fukui

Rina Tanaka

Tomoaki Ishida

Moriaki Akazawa

Shigenori Sakamori

Yoichiro Tarui

Nobuyuki Yoshioka

Kaoru Motonami

Hidetada Tokioka

Takanori Tanaka

Katsutoshi Sugawara

Toshiaki Ogawa

Satoshi Iida

Kensuke Taguchi

Tetsuhiro Fukao

Masayuki Furuhashi

Hiroshi Morita

Satoshi Ogino

Akira Yamashita

Makoto Nagano

Kazuyuki Ohmi

Yoshihiro Kusumi

Takahiro Hoshiko

Hiroshi Miyatake

Naoyuki Kawabata

Akemi Teratani

Takashi Watadani

Yaichirou Watakabe

Katsunobu Hori

Yuzo Irie

The present disclosure relates a semiconductor device using a super junction structure, and includes: a semiconductor base body of a first conductivity type; a pillar part including a plurality of first pillars of a first conductivity type and a plurality of second pillars of a second conductivity type provided on the semiconductor base body to protrude in a thickness direction of the semiconductor base body; a pillar surrounding part of a first conductivity type or a second conductivity type provided around the pillar part; and a semiconductor element in which the pillar part is provided as an active region, wherein the plurality of first and second pillars have a striped shape in a plan view, and are alternately arranged in parallel to each other in a pillar width direction perpendicular to a longitudinal direction of each of the pillars.

Semiconductor device having a plurality of pillars and method of manufacturing the semiconductor device

A superjunction layer includes first pillars of a first conductivity type and second pillars of a second conductivity type. First wells are provided respectively on the second pillars to reach the first pillars and are of the second conductivity type. First impurity regions are provided respectively on the first wells and are of the first conductivity type. Second wells are provided respectively on the first pillars, spaced from the second pillars in a section of an active region that is perpendicular to a semiconductor layer, and are of the second conductivity type. Second impurity regions are provided respectively on the second wells and are of the first conductivity type.

Semiconductor device including an active region that includes a switchable current path

A thermoelectric converter includes a substrate and two thermoelectric elements that may include a flat portion and a concave portion. The thermoelectric elements each include one end that contacts with the thermoelectric element and an other end that contacts with thermoelectric element at a bottom surface of the concave portion. The thermoelectric elements are each positioned to be suspended across a space defined by the concave portion. The thermoelectric converter can be manufactured through photolithographic process, and can be incorporated into an exhaust gas recirculation device.

Thermoelectric converter and manufacturing method for manufacturing thermoelectric converter

A trench-gate semiconductor device including an outside trench, increases reliability of an insulating film at a corner of an open end of the outside trench. The semiconductor device includes: a gate trench reaching an inner part of an n-type drift layer in a cell region; an outside trench outside the cell region; a gate electrode formed inside the gate trench through a gate insulating film; a gate line formed inside the outside trench through an insulating film; and a gate line leading portion formed through the insulating film to cover a corner of an open end of the outside trench closer to the cell region, and electrically connecting the gate electrode to the gate line, and the surface layer of the drift layer in contact with the corner has a second impurity region of p-type that is a part of the well region.

Semiconductor device having a gate trench and an outside trench

A silicon carbide semiconductor device includes trenches formed in a lattice shape on the surface of a silicon carbide substrate on which a semiconductor layer is formed, and gate electrodes formed inside of the trenches via a gate insulating film. The depth of the trenches is smaller in a portion where the trenches are crossingly formed than in a portion where the trenches are formed in parallel to each other. Consequently, the silicon carbide semiconductor device is obtained that increases a withstand voltage between the gate electrodes and corresponding drain electrodes on the semiconductor device rear surface to prevent dielectric breakdown and, at the same time, has a large area of the gate electrodes, high channel density per unit area, and low ON resistance.

Silicon carbide semiconductor device and manufacturing method therefor

A hard mask material such as a silicon oxide film is formed on an aluminum alloy film . The hard mask material is patterned in the form of a thick film wiring , followed by etching the aluminum alloy film to a given depth through the mask. A resist applied to the thin film portion of the aluminum alloy film is patterned in the form of a thin film wiring . Etching through the resist and the hard mask material as a mask is effected to form the thick film wiring and the thin film wiring in the same layer.

Semiconductor device having a layered wiring structure with hard mask covering

A gate electrode includes a polycrystalline silicon layer, a barrier layer and a metal layer. The metal layer and barrier layer includes for example W and RuO,layers, respectively. In forming the gate electrode, the metal layer and barrier layer are etched using at least one of the barrier layer and polycrystalline silicon layer as an etching stopper.

Semiconductor device and manufacturing method thereof

Provided are a method for manufacturing contact structure to prevent, in the wire of a borderless structure, erosion in the contact area between the wire and a conductor. An interlayer insulating film (300) having a wire burying hole is formed and a conductor (400) is buried in the hole. Then, a wire layer (500) covering the hole is formed on the interlayer insulating film (300). The wire layer (500) is made so as to have a borderless structure by using a resist (540) as a mask. A barrier metal layer (510) suppresses erosion in the contact area between the conductor (400) and the wire layer (500).

Method for manufacturing contact structure

Electric field E is generated radially between reaction container and bar-shaped electrode, magnetic field B is formed perpendicular to the electric field, and wafer is disposed perpendicular to magnetic field B. Therefore, the E.times.B drift of plasma generated by magnetron discharge is in the tangential direction of a circle centered at bar-shaped electrode and is parallel to the surface of wafer, whereby maldistribution of plasma in the radial direction is restricted and plasma is distributed uniformly above the main surface of the wafer.

Plasma reaction apparatus

According to a semiconductor device and a method of manufacturing thereof, a sidewall spacer is formed at a sidewall of a contact hole, in a recess portion defined by the sidewall of the contact hole and a buried conductive layer, having a film thickness gradually increasing from a top face corner of an interlayer insulation film to the surface of the buried conductive layer. Therefore, a semiconductor device that can achieve favorable breakdown voltage and anti-leak characteristics between a lower electrode layer and an upper electrode layer forming a capacitor of a DRAM.

Method of manufacturing a semiconductor device having a capacitor

Semiconductor device and a method of manufacturing thereof

Method of manufacturing a semiconductor device with high dielectric

Semiconductor device with high dielectric capacitor having sidewall

A method of electron cyclotron resonance plasma etching including generating a constant plasma in a gas in a chamber containing a semiconductor wafer by supplying microwave energy to the chamber continuously and applying a pulsed direct current bias to the semiconductor wafer, wherein the pulsed bias has a period substantially equal to a time constant determined by the capacitance of the semiconductor wafer and the resistance of an ion sheath at the surface of the semiconductor wafer.

Method of plasma etching

Fine processing is performed by using gas which contains halogen in such a manner that halogen ions contributing to an etching process and ions of a light element, the mass of which is smaller than that of the halogen ion and which does not react with a semiconductor wafer, are present in a plasma generated due to electron cyclotron resonance. Since energy in the plasma is in inverse proportion to the mass, the disorder motion of the halogen ions having large mass can be restrained. Therefore, the halogen ions can be made perpendicularly incident upon the surface of the semiconductor wafer. Consequently, etching process revealing high anisotropy can be performed.

Method of etching a wafer having high anisotropy with a plasma gas

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Tokyo, Japan

Nobuo Fujiwara