Hitachi, Ltd.

Hitachi Information Control Systems, Inc.

Nobuo Akeura

Yoshihiro Miyazaki

Shinichiro Yamaguchi

Soichi Takaya

Koji Matsuda

Naoto Miyazaki

Satoru Kayukawa

Hiroshi Oguro

Kazuhiro Hyuga

Masataka Hiramatsu

A fault-tolerant computer system, which prevents an I/O fault from reaching the CPU block while using an alternative I/O block to continue processing, employs common general-purpose processors with a minimum of specialized peripheral circuits. Dual system bus adapters are provided not in the fast-operating CPU portion requiring sophisticated packaging technology, but in the low-speed interface between the CPUs and the I/O bus adapters. This allows the CPUs and I/O bus adapters to be shared by ordinary data processors, workstations, or personal computers while implementing a fault-tolerant computer system. If a one-shot hardware fault occurs in a CPU or in an I/O bus adapter, the faulty component is disconnected from the system so that the system will operate uninterruptedly.

Fault-tolerant computer system

A method of verifying operation concurrence in maintenance/replacement of twin CPUs employed in a dual-CPU computer wherein a replacement CPU with an initial fault may have been installed by mistake during on-line maintenance/replacement work and a system therefor are disclosed whereby a failure which, without the method and the system, would occur due to the initial fault of the replacement CPU during a dual subsystem synchronous operation carried out thereafter by the computer can be prevented from entailing a system down on both the subsystems.

Method of and system for verifying operation concurrence in

Growing community of inventors

Ebina, Japan

Nobuo Akeura