Matsushita Electric Industrial Co., Ltd.

Nobuki Tominaga

Nobuo Higaki

Shinya Miyaji

Shuichi Takayama

Seiichi Urushibara

Akira Tanaka

Shusuke Haruna

Tomokazu Kanamaru

Masato Suzuki

Kazushi Yamamoto

Yoshito Nishimichi

Takashi Asano

Junko Irimajiri

A program distribution system capable of discarding a distributed program according to the properties of the program is provided. In the program distribution system, a program is distributed from a program transmission apparatus to a program reception terminal over a network. The program transmission apparatus includes a transmission processing section. The program reception terminal includes a reception-side storage section and a discard processing section. The transmission processing section transmits a program and discarding procedure information to the program reception terminal. The discarding procedure information relates to a procedure of discarding the program performed by the program reception terminal. The reception-side storage section stores the program transmitted from the transmission processing section. The discard processing section discards the program stored in the reception-side storage section according to a discarding procedure specified by the discarding procedure information transmitted from the transmission processing section.

Program distribution system for discarding program on reception terminal side

A program conversion apparatus that converts a source program to an executable program, the source program including a first descriptor indicating dynamic memory allocation. The program conversion apparatus includes a specifying unit and a generating unit. The specifying unit specifies in the source program a reference descriptor that is last to be executed from reference descriptors indicating references to memory allocated by the first descriptor. The generating unit generates an instruction for freeing the allocated memory at a position in the executable program immediately following an instruction that corresponds to the specified reference descriptor.

Program conversion apparatus for eliminating unnecessary indications of dynamic memory allocation from a source program and generating an executable program

Java bytecode for having home appliances perform a cooperative operation is developed by a development computer and is sent via a communications satellite from the development computer to a TV tuner&home server provided in a home. After the TV tuner&home server receives the Java bytecode, a bytecode converting unit of the TV tuner&home server determines which home appliance is the target appliance of the Java bytecode and converts the Java bytecode into native code for the microprocessor provided in the target appliance. The native code is downloaded into the target appliance via a home appliance network and the target appliance executes the downloaded native code.

System for distributing native program converted from Java bytecode to a specified home appliance

A program conversion apparatus includes: a library call instruction detecting unit for detecting each library call instruction included in an inputted object program, the library call instruction calling a source library that is an external program module; a library correspondence table that gives various information, such as correspondence between arguments of source libraries and arguments of target libraries that have the same feature as the source libraries and are called by an outputted object program; a library call instruction generating unit for converting the detected library call instruction into an instruction that calls a target library corresponding to the source library and converting instructions for setting the arguments of the source library into instructions for setting arguments of the target library by referring to the library correspondence table.

Program conversion apparatus

The present invention discloses a resource allocation device comprising a pattern generation unit for generating every pattern of a live variable placing within a program portion subjected to resource allocation and a resource to which the live variable is allocated; an instruction extraction unit for extracting from an instruction storage an instruction sequence corresponding to a combination of an operation placing within the program portion and the resource to which a variable in the operation is allocated, and generating a program comprising the extracted instruction sequences; a cost table for memorizing each instruction sequence and cost thereof which represents the number of execution clocks taken in execution of the instruction sequence; a cost detection unit for detecting the cost of each instruction sequence included in the program from the cost table; a total cost detection unit for summing the cost of each instruction sequence detected by the cost detection unit for each pattern generated by the pattern generation unit; and a best pattern decision unit for deciding the pattern with the lowest cost in all the patterns generated by the pattern generation unit.

Resource allocation device for reducing the size and run time of a machine language program

A processor detects a function which includes no function call instruction and no update of the return address /calculation register from an assembler program. After the detection, the processor outputs a special return address to the end of the function detected, and executes the assembler program. The processor stores a return address not only on the stack but in the return address/calculation register. When the special return instruction has been fetched, the return address is moved from the return address/calculation register without accessing to the stack.

Processor which returns from a subroutine at high speed and a program translating apparatus which generates machine programs that makes a high-speed return from a subroutine

A program translating apparatus is composed of a translation unit 103 and a link unit 108. The translation unit 103 includes a determination unit 105 which detects the stack size to be needed for each subroutine included in a source program to be translated into a machine instruction sequence and the name of a register to be retrieved in the process of each subroutine. The determination unit 105 then stores the stack size and the name detected into a file together with the machine instruction sequence. The link unit 108 includes the following units: A branch instruction detection unit 109 detects a branch instruction from the machine instruction sequence when machine instruction sequences stored in different files are linked each other. A file detection unit 110 and an acquisition unit 111 retrieve the stack size and the register name from the file which has the branch target subroutine. A subroutine call instruction generation unit 112 replaces the branch instruction with an instruction which consequently executes a branch operation, a stack reservation, and register retrieval.

Program translating apparatus and a processor which achieve high-speed

The present data processing apparatus effects the pipeline operation for each of the machine cycle time with a plurality of pipeline stages processed in parallel. With respect to a load & extension instruction for instructing with the single instruction a first processing portion for reading the data shorter than the register length from RAM 19 and a second processing portion for zero-extending or the sign-extending the data into the register length, a zero-extension or a sign-extension operation in the second processing operation is executed, in a pipeline stream different from the pipeline stream where a first processing operation is executed or in a pipeline stage different from the pipeline stage where the reading from the storage portion of the first processing operation is executed.

Data processing apparatus for performing a pipeline operation on a load

A compiler comprises a loop detecting unit for extracting information of loops, and a high-speed loop applying unit generating a first loop exclusive instruction, placing the instruction immediately before the entry of a loop, generating second loop exclusive instructions, and placing the instruction at each place to branch to the entry of the loop. A processor comprises: a pipeline comprising: an instruction fetching unit, an instruction decoding unit, and an executing unit; a branch target storage unit; a branch target registering unit for, after the instruction decoding unit has decoded a first loop exclusive instruction, registering branch target information of an instruction succeeding to the first loop exclusive instruction in the branch target registering unit; and a branch executing unit for, after the decoding unit has decoded a second loop exclusive instruction, judging whether to execute a loop, if judges to execute, reading the branch target information registered in the branch target storage unit, and controlling the pipeline so that the program executes the loop using the read branch target information.

Compiler and processor for processing loops at high speed

An information processing apparatus for executing a program, the apparatus including: a register set made up of a plurality of registers; a decoding unit for decoding machine language instructions in the program and extracting a selected instruction which indicates data transfer between a plurality of registers designated by a first operand, which is made up of a single field of at least one bit which shows whether an individual register out of the register set is designated and a group field which shows whether a plurality of other registers out of the register set are designated as a group, and consecutive addresses of memory designated by a second operand as an effective address of memory; a determining unit for determining whether each bit in the single field and group field of the first operand of the extracted machine language instruction is valid; a first generating unit for generating a register number for a register corresponding to a bit determined as being valid in the single field, a second generating unit for generating in order a register number of each register to which the group field relates, when a bit in the group field has been determined as being valid; and a transferring unit for executing data transfer between the registers identified by the register numbers generated by the first generating unit and the second generating unit and the consecutive memory areas starting from the effective address.

Information processing apparatus for realizing data transfer for a

A resource assignment apparatus for use with a software compiler or translator for compiling or translating a high-level source program into a machine language program, wherein the resource assignment apparatus assigns the variables in the high-level source program to system resources consisting of registers, memory, and the like. The resource assignment apparatus generates assignments consisting of the variables and their live ranges and finds the interference cost incurred when assigning these various assignments to each of the various resources, consisting of data registers, address registers, memory, and the like. The apparatus sorts the assignments into groups whereby these interference costs will be the lowest. The resource element minority assignment unit then carries out the assigning of each of these groups of sorted assignment. The various assignments with live ranges which interfere are assigned to different resource elements. When there are a number of resource elements to which an assignment can be assigned, the apparatus determines which is the most appropriate resource element, and assigns the assignment to this most appropriate resource element. When there is no resource element for which assigning is possible, the assignment is then moved to another resource group.

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Kyoto, Japan

Nobuki Tominaga