Nec Corporation

Nec Electronics Corporation

Nobuki Kajihara

Takeshi Inuo

Masato Motomura

Taro Fujii

Takao Toi

Kenichiro Anjo

Hirokazu Kami

Tooru Awashima

Kengo Nishino

Kouichiro Furuta

Koichiro Furuta

A computing section is provided with a plurality of computing units and correlatively stores entries of configuration information that describes configurations of the plurality of computing units with physical configuration numbers that represent the entries of configuration information and executes a computation in a configuration corresponding to a designated physical configuration number. A status management section designates a physical configuration number corresponding to a status to which the computing section needs to advance the next time for the computing section and outputs the status to which the computing section needs to advance the next time as a logical status number that uniquely identifies the status to which the computing section needs to advance the next time in an object code. A determination section determines whether or not the computing section has stored an entry of configuration information corresponding to the status to which the computing section needs to advance the next time based on the logical status number that is output from the status management section. A rewriting section correlatively stores the entry of the configuration information and a physical configuration number corresponding to the entry of the configuration information in the computing section when the determination section determines that the computing section has not stored the entry of configuration information corresponding to the status to which the computing section needs to advance the next time.

Indirect designation of physical configuration number as logical configuration number based on correlation information, within parallel computing

A network switch transfers data, which are to be transferred between nodes, in a time-division multiplex manner after allocating the data to slots, which are created by dividing a unit of time into a plurality of sections. An input unit includes a selection unit that selects a buffer unit according to an input slot in order to transfer the data input from the input port to the buffer unit, an input slot correspondence management table that stores a correspondence relationship between the input slots and the buffer units, and input port management information used to control a communication bandwidth of the input port. An output unit includes a multiplexing unit that selects the buffer unit according to an output slot in order for data, which is to be output to the output port, to be transferred from the selected buffer unit to the output port, an output slot correspondence management table that stores a correspondence relationship between the output slots and the buffer units, and output port manage information used to control a communication bandwidth of the output port.

Interprocessor communication system and communication method, network switch, and parallel calculation system

A parallel calculation system includes a plurality of functional nodes and a plurality of network switches, which serve as part of a communication path for communication between the functional nodes and function as communication channels. As for the functional nodes, a functional node group made up of part or all of a plurality of the functional nodes that the parallel calculation system includes is managed as one group. The network switches include a plurality of input/output ports, which are ports for inputting and outputting the communication request, and a switch, which outputs the communication request that the input/output port inputs to the input/output port. The network switches manage a communication bandwidth for each of the communication channels between the functional nodes and control the switch.

Parallel calculation system, and method and program thereof

A data processing device comprises a state manager for determining a logic number of configurational information to be used in a next state, the logic number representing information on a mutual relationship between items of configurational information included in an object code, based on a present operational state, a group of candidates for a state to transit to next, and an event signal issued from arithmetic units, a configuration number converter for outputting a real number corresponding to the logic number determined by the state manager, the configuration number converter having conversion information for converting the logic number into a real number representing a location where the corresponding configurational information is actually stored, and a configurational information storage for storing the configurational information and indicating configurational information corresponding to the real number output from the configuration number converter, to the arithmetic units and an interconnector.

Converting logical to real number to access shared configuration information in event driven state transiting reconfigurable system

Configuration codes for implementing a plurality of circuits having different attributes are generated and stored in a memory for each task executed in a reconfigurable device. When the reconfigurable device is operated, an appropriate circuit to be executed by the reconfigurable device is selected in accordance with an operation state of the system from among a plurality of circuits having different attributes, and the configuration code for implementing the selected circuit is loaded from the memory into the reconfigurable device.

Information processing apparatus and method for using reconfigurable device

An array-type computer processor including a data path unit communicating with a state control unit obtains data of a predetermined number of cooperative partial instruction codes, and operates with temporarily holding only a predetermined number of data-obtained instruction codes comprising cooperative partial instruction codes corresponding to contexts and operation states for the data path unit and the state control unit, respectively, from an external program memory which stores data of a computer program. Every time the operations with the temporarily-held instruction codes, including the corresponding cooperative partial instruction codes, are complete, in accordance with event data entered in the state control unit, the subsequent instruction codes are data obtained as cooperative partial instruction codes respectively corresponding to contexts and operating states, so that the operation according to a computer program can be performed even if the data volume of the computer program is over the storage capacity of the data path unit and the state control unit.

Array&#x2014;type computer processor with reduced instruction storage

An array-type computer processor stops, with a plurality of computer programs held, a state control unit and a data-path unit, upon input of event data for task switching. The array-type computer processor obtains the operation state of the state control unit and the processed data of the data-path unit when stopped, and temporarily holds them for each of a plurality of the computer programs. Upon completion of this, the array-type computer processor reads the operation state and processed data of any other computer program and sets them in the state control unit and data-path unit. Upon completion of this, the array-type computer processor outputs to the state control unit the event data for starting the operation. The state control unit then starts to sequentially transfer the operation state, thereby making it possible to perform the process operations according to a plurality of computer programs in a time-sharing manner.

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Tokyo, Japan

Nobuki Kajihara