Lapis Semiconductor Co., Ltd.

Oki Semiconductor Co., Ltd.

Oki Electric Industry Co., Ltd.

Nobukazu Murata

Katsuaki Matsui

Teruhiro Harada

Hiroyuki Tanikawa

Tomonori Terasawa

A majority voting processing device performs majority voting on respective bits of information data piece including r-number of bits (r is an integer of 2 or greater). The device includes a memory including a plurality of memory element groups each including r-number of memory elements that store data for the corresponding r-number of bits, respectively, the plurality of memory element groups each being provide for one address. A memory access unit writes each bit of the information data piece in k-number (k is an odd number of 3 or greater) of the memory elements in the memory element group corresponding to one address, and reads out the k-number of bits written in the k-number of the memory elements corresponding to that one address. A majority voter that performs majority voting on the k-number of bits read out from the memory by the memory access unit.

Majority voting processing device, semiconductor memory device, and majority voting method for information data

The present disclosure provides a semiconductor memory including a first capacitor, a second capacitor, and a transistor. The first capacitor includes a first conductive layer provided on a surface of an n-well, n-type diffusion layers provided in a surface layer portion of the n-well, and a p-type diffusion layer provided in the surface layer portion of the n-well so as to be adjacent to the first conductive layer and separated from the n-type diffusion layers. The second capacitor includes a second conductive layer provided on a surface of an n-well, n-type diffusion layers provided in a surface layer portion of the n-well, and a p-type diffusion layer provided in the surface layer portion of the n-well so as to be adjacent to the second conductive layer and separated from the n-type diffusion layers.

Semiconductor memory and semiconductor memory manufacturing method

On the basis of data addresses indicative of write bit positions of each of the write data pieces in each of blocks, write page addresses indicative of pages having each of the write data pieces written thereto in each of the blocks are detected. At least one write data piece is incorporated into each of the page data pieces indicated by the write page addresses among k page data pieces corresponding to the k pages, the page data pieces having the write data pieces incorporated therein are used as page data pieces, and an error-correction encoding process is applied to each of the write page data pieces to obtain encoded write data pieces. Then, a voltage based on the encoded write data pieces is applied to each of the memory cells belonging to the pages indicated by the write page addresses.

Semiconductor memory system and data writing method

A charge pump circuit includes a first capacitor and a second capacitor to which respective pulse signals are input; a first transistor including a source connected to a voltage input terminal, a drain connected to the first capacitor and a gate connected to the second capacitor; a second transistor including a source connected to the voltage input terminal, a drain connected to the second capacitor and a gate connected to the first capacitor; and a potential fixing circuit provided between a first node that is a connection node of the first transistor and the first capacitor, and a second node that is a connection node of the second transistor and the second capacitor. The potential fixing circuit fixes a potential of the first node to a potential according to a potential of the second node.

Charge pump circuit and boosting circuit

The present invention provides a row decoder of a semiconductor storage device that prevents an increase in a circuit area while maintaining a high operation speed. Namely, the row decoder of the semiconductor storage device includes a word line selection circuit that has voltage application MOS transistors for each of plural word lines, the voltage application MOS transistors applying a normal voltage to the word lines corresponding to memory cells selected among plural memory cells positioned at a portion where the plural word lines intersect plural bit lines in a predetermined normal operation, and applying a high voltage in a predetermined high voltage operation; and a level shift circuit that outputs the normal voltage or a ground voltage lower than the normal voltage in the normal operation, and that outputs the normal voltage or the high voltage in the high voltage operation, to the voltage application MOS transistor.

Decoder circuit of semiconductor storage device

The present invention provides a semiconductor storage circuit that may suppress a data read characteristic from being deteriorated due to influence of characteristic change of a sense amplifier, in a multi-bit-type memory cell. The semiconductor storage circuit includes a memory cell array that has plural multi-bit-type memory cells, two multiplexers, and two sense amplifiers. The first multiplexer connects a main bit line connected to an R-side electrode of the even-numbered memory cell in a row direction to the first sense amplifier, and connects a main bit line connected to an L-side electrode of the odd-numbered memory cell to the second sense amplifier. The second multiplexer connects a main bit line connected to an L-side electrode of the even-numbered memory cell to the first sense amplifier, and connects a main bit line connected to an R-side electrode of the odd-numbered memory cell to the second sense amplifier.

Semiconductor storage circuit

A semiconductor memory circuit includes a memory cell array having a plurality of memory cells arranged in a row direction and a column direction; a row selecting unit for selecting the memory cells of the memory cell array aligned in the row direction; a column selecting unit for selecting the memory cells of the memory cell array aligned in the column direction; a plurality of main bit lines for outputting data of the memory cells; a data reading unit for reading data of one of the memory cells selected with the row selecting unit and the column selecting unit; a first multiplexer for connecting one of the main bit lines connected to the memory cell to the data reading unit; and a second multiplexer for connecting an adjacent main bit line situated adjacently outside the main bit line to a charging/discharging voltage source for setting at a specific voltage.

Semiconductor memory circuit equipped with multiplexer for reducing coupling capacitance of non-selected main bit lines

The present invention provides a readout circuit including: a memory cell array that includes a readout target memory cell that is a data readout target; a reference memory cell having the same configuration as this memory cell; a first constant current source and a second constant current source which have the same characteristics; and a reference current source that generates, as a reference current for determining the logic level of the readout target memory cell, a current obtained by adding one constant current, out of a first constant current flowing through the first constant current source or a second constant current flowing through the second constant current source, with a reference memory cell current flowing in the reference memory cell, and by subtracting the other constant current, out of the first constant current or the second constant current, from the added current.

Nonvolatile semiconductor storage device

A data readout circuit including a 1st PMOS transistor operating in saturation and including a source connected to a power supply, a drain connected to an input terminal a memory cell, and a gate connected to a 1st bias voltage; a 2nd PMOS transistor including a source connected to the drain of the 1st PMOS transistor, a drain connected to an output terminal, and a gate connected to a 2nd bias voltage; a 1st NMOS transistor including a drain connected to the drain of the 2nd PMOS transistor, a source grounded, and a gate connected to a 3rd bias voltage; and a bias voltage section causing the 2nd PMOS transistor to operate in saturation, and supplying the 2nd bias voltage adjusted so as to keep a reference voltage of the input terminal at a junction point between the drain and the source of the 1st and 2nd PMOS transistors respectively.

Data readout circuit and semiconductor memory device

A current source device that cuts off an output current when stopped and obtains a desired output current upon start-up includes a first circuit having a first FET and resistors in series, a second circuit having second and third FETs in series with a point between the second and third FETs and a gate of the third FET connected, a drive circuit supplying a common drive voltage to gates of the first and second FETs, and first and second current source circuits responsive to first and second drive voltages that are gate voltages of the second and third FETs. The first and second current source circuits respectively include first and second current source FETs having the first and second drive voltages as gate voltages, and a start-up circuit changing the first and second drive voltages forcedly when the first and second current source FETs are made conductive.

Current source device, oscillator device and pulse generator

A memory cell array includes a plurality of memory cells disposed in matrix. A plurality of word lines extend in the row direction, and the gates in the memory cells disposed in each row are commonly connected to one of the word lines. A plurality of sub bit lines extend in the column direction, and the sources in the memory cells disposed in a first column and the drains in the memory cells disposed in a second column, which is adjacent to the first column, are commonly connected to one of the sub bit lines. A plurality of pairs of transistors are provided, each having a source selector and a drain selector. Each transistor pair is disposed at one of the locations at both ends of the sub bit lines, which are adjacent to each other, in a manner such that the transistor pairs sandwich the word lines from alternating sub bit ends.

Memory cell array and semiconductor memory

In a semiconductor nonvolatile memory, plural first nonvolatile memory cells are arranged in the memory array. Plural memory areas are arranged in the memory array and have plural second nonvolatile memory cells which store the same predetermined information. A sequence circuit generates a memory address, a latch selection signal, and a control signal at predetermined timings when a power is turned on. A write-read unit writes and reads information to and from the memory array and the memory areas based on the memory address and the control signal. A latch circuit latches the predetermined information, read by the write-read unit, based on the latch selection signal. A selection-drive unit selects the first or second nonvolatile memory cells based on the memory address and the predetermined information latched by the latch circuit, and applies a predetermined voltage to drive the selected first or second nonvolatile memory cells.

Semiconductor nonvolatile memory trimming technique for output characteristic control and redundancy repair

A high-speed nonvolatile memory array has two-bit memory cells, each connected to a mutually adjacent pair of sub-bit lines. The sub-bit lines are connected to a common power supply line through switching elements controlled in a cyclic sequence by 2m signal lines, where m is an integer greater than one. The memory array circuit also has main bit lines, each connected to a group of m consecutive sub-bit lines through switching elements controlled in a cyclic sequence by m signal lines. Data are read through two mutually adjacent main bit lines from two memory cells selected so that the sub-bit lines connecting the two main bit lines to the two memory cells are located between the sub-bit lines connecting the two memory cells to the common power line, an arrangement that reduces parasitic capacitance.

Growing community of inventors

Tokyo, Japan

Nobukazu Murata