Nec Corporation

Nec Electronics Corporation

Nobukazu Ito

Yasutaka Nakashiba

Hiroaki Ohkubo

Naoki Oda

Hiroshi Murase

Tokuhito Sasaki

Naoyoshi Kawahara

Yoshihisa Matsubara

Kuniko Kikuta

Kazumi Sugai

Yoshiaki Yamada

Kazuyoshi Ueno

Kuniko Miyakawa

Hiroaki Tachibana

Michiko Yamanaka

In a temperature sensor section of a semiconductor integrated circuit device, wires of the topmost wiring layer of a multi-layer wiring structure are formed. A sheet-like temperature monitor element of vanadium oxide is provided between two of the wires in such a way as to cover the two wires. Accordingly, the temperature monitor element is connected between the two wires of an underlying wiring layer of the multi-layer wiring structure through two vias and the two wires of the topmost wiring layer.

Integrated circuit device and fabrication method therefor

In a semiconductor integrated circuit device, a logic circuit section is provided at the top surface of a P-type silicon substrate and a multi-level wiring layer. The device is further provided with a temperature sensor section in which a first temperature monitor member of vanadium oxide is provided above the multi-level wiring layer. A second temperature monitor member of Ti is provided at a lowermost layer of the multi-level wiring layer. The first and second temperature monitor members are connected in series between a ground potential wire and a power-source potential wire, with an output terminal connected to the node of both members. The temperature coefficient of the electric resistivity of the first temperature monitor member is negative, while that of the second temperature monitor member is positive.

Integrated circuit device with temperature monitor members

A vanadium oxide film is formed on an interlayer insulating layer, and a silicon oxide film and a silicon nitride film are formed on the vanadium oxide film in this order. With a resist pattern used as a mask, the silicon nitride film is patterned. Then, the resist pattern is removed using a stripping solution or oxygen plasma ashing. Next, with the patterned silicon nitride film used as a mask, the silicon oxide film and the vanadium oxide film are etched to form a resistor film of vanadium oxide.

Integrated circuit device, method of manufacturing the same and method of forming vanadium oxide film

In a semiconductor integrated circuit device, a sheet-like temperature monitor member of vanadium oxide is provided, whose one end is connected to one via while the other end is connected to another via. A sheet-like thermal conducting layer of aluminum is provided below the temperature monitor member. A region equal to or greater than a half of the entire temperature monitor member overlies the thermal conducting layer in a plan view.

Integrated circuit including a temperature monitor element and thermal conducting layer

In a temperature sensor section of a semiconductor integrated circuit device, first vias of tungsten are formed at the topmost layer of a multi-layer wiring layer and pads of titanium are provided on regions of the multi-layer wiring layer which covers the vias. An insulating layer is provided in such a way as to cover the multi-layer wiring layer and the pads, second vias are so formed as to reach the pads. Vanadium oxide is buried in the second vias by reactive sputtering, and a temperature monitor part of vanadium oxide is provided in such a way as to connect the second vias each other. Accordingly, the temperature monitor part is connected between the two wires.

Integrated circuit device

There is presented a semiconductor device including multiple levels of copper interconnects; wherein the surface of a copper interconnect corresponding to at least one underlying layer of another copper interconnect layer is turned into copper oxide to a thickness of 30 nm or more by oxidation conducted at the oxidation rate of 20 nm/min or less, and thereby the reflection of the exposure light from the lower-level copper interconnect is prevented, in forming by means of photolithography a trench to form a copper interconnect through damascening.

Semiconductor device and manufacturing method thereof

A method of forming a multi-layer structure over an insulating layer comprises the steps of: selectively depositing a barrier layer on a predetermined region of an insulating layer by use of a first deposition mask; selectively depositing a metal seed layer made of a metal which is different in substance from the barrier layer by use of a second deposition mask, so that the metal seed layer extends not only on an entire surface of the barrier layer but also a peripheral region positioned outside the predetermined region of the insulating layer; and forming a metal plating layer made of the same metal as the seed layer, so that the metal plating layer is adhered on the metal seed layer whereby the metal plating layer is separated from the barrier layer and also from the insulating layer.

Method of forming a semiconductor device and an improved deposition system

A manufacturing method of a semiconductor device which includes wiring dense part and wiring isolated part enables occurrence of 'Erosion' to be prevented, as well as it is capable of being prevented occurrence of 'micro-scratch' on surface of oxide layer. The manufacturing method sets a plurality of trench-parts on insulation layer, before forming metal plating layer consisting of copper so as to embed trench-parts. Manufacturing process implements annealing in such a way that grain-size of the metal plating layer in the wiring dense part becomes smaller than the grain-size in the wiring isolated part. The annealing, for instance, is implemented with substrate temperature of 70 to 200&deg; C. Subsequently, the manufacturing step perfects the semiconductor device while polishing the metal plating layer to cause the surface of the substrate to be flat.

Method of improving the planarization of wiring by CMP

A method of forming a multi-layer structure over an insulating layer comprises the steps of: selectively depositing a barrier layer on a predetermined region of an insulating layer by use of a first deposition mask; selectively depositing a metal seed layer made of a metal which is different in substance from the barrier layer by use of a second deposition mask, so that the metal seed layer extends not only on an entire surface of the barrier layer but also a peripheral region positioned outside the predetermined region of the insulating layer; and forming a metal plating layer made of the metal of the metal seed layer, so that the metal plating layer is adhered on the metal seed layer whereby the metal plating layer is separated from the barrier layer and also from the insulating layer.

Method of forming a semiconductor device

There is presented a semiconductor device including multiple levels of copper interconnects; wherein the surface of a copper interconnect corresponding to at least one underlying layer of another copper interconnect layer is turned into copper oxide to a thickness of 30 nm or more by oxidation conducted at the oxidation rate of 20 nm/minor less, and thereby the reflection of the exposure light from the lower-level copper interconnect is prevented, in forming by means of photolithography a trench to form a copper interconnect through damascening.

Method of forming multi-level copper interconnect with formation of copper oxide on exposed copper surface

In a process for manufacturing a semiconductor device where a plurality of wafers are formed on a single wafer, comprising the steps of forming a groove pattern in an insulating layer on a wafer; forming a seed metal layer in the groove by spattering; depositing an interconnection metal layer on the seed metal layer by electrolytic plating; and then flattering the wafer to the surface of the insulating layer, during forming the groove pattern in the insulating layer, the groove pattern is formed in the area on the wafer where devices can be taken while forming a dummy pattern up to 30 &mgr;m long in the wafer periphery where devices cannot be taken, to prevent the interconnection metal layer from being peeled in the wafer periphery.

Process for manufacturing semiconductor device and exposure mask

The present invention discloses a process for manufacturing a semiconductor device in which characteristics of an aluminum alloy film are prevented from deteriorating, when a titanium film is used as an under film and the aluminum alloy film is heated to fill a via hole therewith. Interlayered insulating film is formed on a first aluminum wire, and after the formation of a via hole which reaches the first aluminum wire, a titanium film and an aluminum alloy film are formed in turn by a sputtering process. Next, a silicon substrate is heated up to 450.degree. to 500.degree. C. to melt the aluminum alloy film, thereby filling the via hole therewith. In this case, the thickness of the titanium film is set to 10% or less of the thickness of the aluminum alloy film and at most 25 nm. In particular, in the case of the aluminum alloy film containing no silicon, the thickness of the titanium film is set to 5% or less of the thickness of the aluminum alloy film, whereby the deterioration of characteristics of the aluminum alloy film by titanium can be minimized, and the via hole can be surely filled therewith.

Process of manufacturing a semiconductor device by filling a via hole in

The present invention relates to a method of fabricating a semiconductor device, which comprises a formation of contact holes in an interlayer insulating film formed on a silicon substrate, formation of a titanium film and a titanium nitride film, as a barrier metal, and lamp annealing. The formation of the titanium nitride film is featured by reactive sputtering using a titanium target whose orientation ratio of (001) plane is not more than 70%. The titanium nitride film thus formed does not shrink rapidly during heat treatment and thus degradation of barrier performance thereof is prevented.

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Tokyo, Japan

Nobukazu Ito