Toshiba Memory Corporation

Kabushiki Kaisha Toshiba

Kioxia Corporation

Nec Electronics Corporation

Nobuhiro Tsuji

Shinya Takeda

Shunsuke Kodera

Yoshio Furuyama

Toshihiko Kitazume

Tetsuya Iwata

Hirosuke Narai

Kenichirou Kada

Masashi Nakata

Yohei Yasuda

Hiroki Ohkouchi

Shota Note

Mikio Takasugi

According to one embodiment, there is provided a semiconductor device including a first chip, a second chip group having a plurality of second chips electrically connected to the first chip, and a third chip group having a plurality of third chips electrically connected to the first chip in parallel with the second chip group, in which the first chip has a command queue that stores a plurality of read commands received from the host, and a read buffer memory that buffers read data, sequentially issues the plurality of read commands stored in the command queue to the second chip group or the third chip group, stores the read data corresponding to the plurality of read commands from the second chip group or the third chip group, in the read buffer memory, and transmits any read data among the read data stored in the read buffer memory to the host based on an execution status of any read command among the plurality of read commands.

Semiconductor device and control method

According to one embodiment, there is provided a semiconductor apparatus including a first chip and a second chip. The first chip is electrically connected to a terminal to which a signal from a host device is input. The second chip is electrically connected to the first chip. The second chip has a first duty adjustment circuit. The first chip has a second duty adjustment circuit. The first duty adjustment circuit performs first calibration operation in a first period. The second duty adjustment circuit performs second calibration operation in a second period. The first period and the second period have an overlapping period.

Semiconductor apparatus and method for controlling semiconductor apparatus

A memory device includes a semiconductor memory unit, a controller circuit configured to communicate with a host through a serial interface, store write data to be written into a page of the semiconductor memory unit in a data buffer, and an error-correcting code (ECC) circuit configured to generate an error correction code from the write data if the ECC circuit is enabled. The controller circuit writes the error correction code with the write data into the page if the ECC circuit is enabled. A maximum column address of the page which is accessible from the host changes depending on whether or not the ECC circuit is enabled.

Memory device that changes a writable region of a data buffer based on an operational state of an ECC circuit

A semiconductor integrated circuit includes a register, a detection circuit, and a generation circuit. The register stores a detection start timing of a reference delay amount based on a first clock during a first period. The first period is a period in which the first clock starts to be input. The detection circuit has a plurality of delay stages. The detection circuit detects the reference delay amount at the start timing during the first period and obtains the number of delay stages corresponding to the reference delay amount. The generation circuit adjusts a duty ratio of the first clock based on the number of delay stages obtained by the detection circuit and generates a second clock during a second period. The second period is a period continuing from the first period.

Semiconductor integrated circuit and semiconductor device

A memory device includes a semiconductor memory unit, a controller configured to communicate with a host through a serial interface and read data stored in a page of the semiconductor memory unit in response to a read command received through the serial interface, and an error-correcting code (ECC) circuit configured to carry out error correction with respect to data read from each unit region of the page. The controller is further configured to transmit, through the serial interface to the host, information that indicates whether or not a number of error bits detected by the ECC circuit in the data read from each unit region of the page through the error correction is greater than a predetermined value.

Memory device that communicates error correction results to a host

A memory system includes a semiconductor memory device including a plurality of blocks, and a controller configured to register a block designated in a protection command as a protected block in a storage region. When the control circuit receives from a host a command to erase the protected block or write to the protected block, the control circuit does not issue a corresponding erase or write command to the semiconductor memory device and notifies the host of the failure to execute the command.

Memory system having a semiconductor memory device with protected blocks

A memory device includes a semiconductor memory unit and a controller circuit configured to communicate with a host through a serial interface and access the semiconductor memory unit in response to commands received through the serial interface. The controller circuit, in response to a host command to read parameters of the memory device, updates at least one of parameters of the memory device stored in the memory device based on operational settings of the memory device, and transmits the updated parameters through the serial interface to the host.

Memory device that updates parameters transmitted to a host based on operational settings

A memory system includes a semiconductor memory device, a controller configured to access the semiconductor module, a plurality of pins for connection to the outside of the memory system, the pins configured to receive and output serial data, and a test circuit. When one of the pins receives serial test data, the test circuit converts the serial test data into parallel test data, and outputs the parallel test data to the semiconductor memory device for writing therein, and when the test circuit receives parallel test data written in the semiconductor memory device, the test circuit converts the parallel test data to serial test data, and outputs the serial test data through one of the pins for test of the memory system.

Memory system including test circuit

A memory system includes first through fifth pins connectable to a host device to output to the host device a first signal through the third pin and to receive from the host device a first chip select signal through the first pin, a second chip select signal through the second pin, a second signal through the fourth pin, and a clock signal through the fifth pin, an interface circuit configured to recognize, as a command, the second signal received through the fourth pin immediately after detecting the first or second chip select signal, and first and second memory cell arrays. The interface circuit and the first and second memory cell arrays are provided in one common package, and is configured to access the first memory cell array when detecting the first chip select signal, and to access the second memory cell array when detecting the second chip select signal.

Memory system

A memory system includes a plurality of pins for connection to the outside of the memory system, one of the pins being configured to receive a command signal, a memory cell array including a plurality of first memory blocks and a second memory block in which status data indicating which of the first memory blocks is defective, is stored, and a control circuit configured to determine whether or not a first memory block targeted by the command signal is indicated as being defective in the status data. The control circuit allows an operation to be performed on the targeted first memory block in accordance with the command signal when the targeted first memory block is not indicated as being defective, and blocks the operation to be performed on the targeted first memory block when the targeted first memory block is indicated as being defective.

Memory system that handles access to bad blocks

A memory device includes a semiconductor memory unit, and a controller configured to communicate with a host through a serial interface and access the memory semiconductor unit in response to commands received through the serial interface. The controller, in response to a first read command received through the serial interface to read data in a first page of the semiconductor memory unit, issues a first command to the semiconductor memory unit to read data in the first page and, in addition, a second command to read data in a second page that is consecutive to the first page and not specified in the first read command.

Growing community of inventors

Yokohama Kanagawa, Japan

Nobuhiro Tsuji