Fujitsu Semiconductor Limited

Fujitsu Corporation

Mie Fujitsu Semiconductor Limited

United Semiconductor Japan Co., Ltd.

Fijitsu Limited

Nobuhiro Misawa

Kenichi Watanabe

Taiji Ema

Makoto Yasuda

Satoshi Otsuka

Kazuyuki Kumeno

Masataka Hoshino

Masashi Shima

Toshiya Suzuki

Kaoru Saigoh

Fumitake Mieno

Tamotsu Yamamoto

Takayuki Ohba

Hideo Takagi

Wataru Futo

Tetsuya Shirasu

Toshiyuki Karasawa

Takao Sasaki

Akio Yamaguchi

Koji Endo

Shigetaka Uji

Tatsushi Hara

Yukihiro Satoh

Kiyoshi Izumi

Yuzuru Ohta

Kenji Nakano

A semiconductor device includes as a resistance element a first polycrystalline silicon and a second polycrystalline silicon containing impurities, such as boron, of the same kind and having different widths. The first polycrystalline silicon contains the impurities at a concentration C. The second polycrystalline silicon has a width larger than a width of the first polycrystalline silicon and contains the impurities of the same kind at a concentration Clower than the concentration C. A sign of a temperature coefficient of resistance (TCR) of the first polycrystalline silicon changes at the concentration C. A sign of a TCR of the second polycrystalline silicon changes at the concentration C.

Method of fabricating semiconductor device having resistance elements

Semiconductor device having resistance elements and fabrication method thereof

The semiconductor device includes a capacitor including a plurality of interconnection layers stacked over each other, the plurality of interconnection layers each including a plurality of electrode patterns extended in a first direction, a plurality of via parts provided between the plurality of interconnection layers and electrically interconnecting the plurality of the electrode patterns between the interconnection layers adjacent to each other, and an insulating films formed between the plurality of interconnection layers and the plurality of via parts. Each of the plurality of via parts is laid out, offset from a center of the electrode pattern in a second direction intersecting the first direction, and the plurality of electrode patterns has a larger line width at parts where the via parts are connected to, and a distance between the electrode patterns and the adjacent electrode patterns is reduced at the parts.

Semiconductor device and method of manufacturing semiconductor device

A method of manufacturing a semiconductor device, including: forming a moisture resistant ring surrounding a multilayer interconnection structure in a layered body formed of stacked layers of a plurality of interlayer insulating films lower in dielectric constant than a SiOfilm and including the multilayer interconnection structure; forming a groove in the layered body between the moisture resistant ring and a scribe line, the groove reaching a surface of a semiconductor substrate; forming a film including Si and C as principal components and covering sidewall surfaces and a bottom surface of the groove; and forming a protection film on the film along the sidewall surfaces and the bottom surface of the groove.

Semiconductor device

A semiconductor device includes a transistor array including a plurality of transistors each having a gate electrode extended in a first direction, the plurality of transistors being arranged in a second direction intersecting the first direction, and a pad electrode arranged in the first direction of the transistor array and electrically connected to source regions of the plurality of transistors.

Semiconductor device including capacitor of interconnection

Method for manufacturing semiconductor device

A semiconductor device includes a substrate; a layered body formed on the substrate and including a multilayer interconnection structure, the layered body including multiple interlayer insulating films stacked in layers, the interlayer insulating films being lower in dielectric constant than a SiOfilm; a moisture resistant ring extending continuously in the layered body so as to surround a device region where an active element is formed; a protection groove part formed continuously along and outside the moisture resistant ring in the layered body so as to expose the surface of the substrate; a protection film continuously covering the upper surface of the layered body except an electrode pad on the multilayer interconnection structure, and the sidewall and bottom surfaces of the protection groove part; and an interface film including Si and C as principal components and formed between the protection film and the sidewall surfaces of the protection groove part.

An electric conductive film is formed on the insulating surface of a substrate, the substrate having a trench formed on the insulating surface, and the conductive film being filled in the trench. Chemical mechanical polishing is executed to expose the insulating surface of the substrate and leave a portion of the conductive film in the trench. The surface of the substrate having the exposed conductive film in the trench and the exposed insulating surface is exposed to first liquid. After being exposed to the first liquid, the surface of the substrate is exposed to second liquid. The first liquid is either solution which contains at least one first substance selected from a first group consisting of benzotriazole, derivative of benzotriazole and interfacial active agent, or water. The second solution is solution which contains the first substance at a density higher than a density of the first liquid.

Semiconductor device manufacture method

The method of manufacturing a semiconductor device includes the steps of forming copper wiring; reducing an oxide film on the surface of the copper wiring by heating the copper wiring to a temperature in a range of 250&deg; C.-450&deg; C. under reductive gas or by treating the copper wiring in plasma of reductive gas; and then forming a film of a material not containing oxygen on the copper wiring without exposing the copper wiring to external atmosphere, and can provide a semiconductor device with good copper wiring.

Semiconductor device with copper wiring and its manufacture method

A process of growing a film of a metal on a substrate in a selective area thereof by chemical vapor deposition, the process comprising the steps of: preparing a source having a molecule comprising a metal and a radical; providing a substrate having a selective area made of a first substance which is unreactive with the radical and the other area made of copper which is reactive with the radical; and supplying the source onto the substrate held at a film growing temperature to induce a reaction on the substrate, such that, in the selective area, the molecule of the source is bonded to the first substance and decomposed to precipitate the metal on the first substance while, in the other area, the radical of the molecule is combined with the copper to cover the other area of the substrate with a coating which is unreactive with the molecule of the source.

Process of selective area chemical vapor deposition of metal films

A process for fabricating an integrated circuit device comprises a first step of forming an opening in an insulating layer formed on a substrate, a second step of depositing a copper layer on the substrate including the opening, a third step of abrading the copper layer to remove the copper layer deposited on the insulating layer, while part of the copper layer deposited in the opening is removed until the upper surface of said part becomes lower than the upper surface of the insulating layer, a fourth step of depositing a barrier layer on the substrate including the copper layer in the opening, and a fifth step of abrading the barrier layer to remove part of the barrier layer on the insulating layer while part of the barrier layer on the copper layer in the opening is left, so as to planarize the surface. A wiring layer of copper can be formed without a conventional step of etching a copper layer to leave a wiring layer. Furthermore, the copper wiring layer is coated by layers of barrier materials, whereby oxidation and diffusion of the copper is precluded with a result that planarized wiring layers of high electromigration resistances and low resistances can be formed.

Process for fabricating integrated circuit devices

A chemical vapor deposition (CVD) system for depositing a material selectively on a part of a substrate comprises a reaction chamber in which a CVD process is performed, a substrate holder and substrate heater provided within the reaction chamber, a gas inlet fixture provided on the reaction chamber for introducing one or more CVD source gases into the reaction chamber, and a reactant distribution fixture provided on the gas inlet fixture within the reaction chamber for controlling distribution of the reactant species in the reaction chamber, wherein the reactant distribution fixture defines a subspace surrounding the substrate within the space of the reaction chamber such that the subspace has a dimension, measured in a direction generally perpendicular to the surface of the substrate such that the dimension is at least less than one half of the mean free path of the reactant species realized inside the space of the reaction chamber during the CVD process and such that an opening is formed for communicating the subspace inside the reaction distribution means with the rest of the space of the reaction chamber for freely passing product species formed as a result of the chemical reaction at the surface of the substrate.

Chemical vapor deposition system

Growing community of inventors

Kawasaki, Japan

Nobuhiro Misawa