Kabushiki Kaisha Toshiba

Nobuhiro Ide

Takeshi Yoshida

Itaru Yamazaki

Junji Mori

Yoshihisa Kondo

Masato Nagamatsu

Maki Ueno

Atsushi Kunimatsu

Hiroyuki Takano

Atsuhi Kunimatsu

A processing apparatus includes a plurality of operation units each of which performs a given operation for an input operand in accordance with an operating instruction and outputs an exception flag when a result of the operation is false, a first network which connects the storage unit which stores the operand and the operation units, a second network which connects the operation units and the storage unit, and a defect sensor which receives the exception flag from each of the operation units to sense an operation unit from which the exception flag is generated with high frequency. The apparatus further includes a logic unit controller which controls the first network and the second network to disconnect the operation unit from a system, and causes another operation unit to perform an operation assigned to the disconnected operation unit again.

Processing apparatus

Floating-point calculator

An internal memory section is divided into plural memory blocks. During a period of time, a relevant memory block of the internal memory section is connected to an external memory unit, while another memory block thereof is connected to a data holding section. During a succeeding period of time, the relevant memory block is connected to the data holding section, while the other memory block is connected to the external memory unit. Data exchange between the data holding section and the external memory unit via the internal memory section is performed while the alternative connection is repeated.

Graphic translate engine, floating point arithmetic unit and floating point multiply-add calculation unit

A floating point multiply-add operating device in which a critical path in an addition process of continuous multiply-add operations of floating point numbers is shortened to improve operation efficiency is disclosed. This operating device includes: an exponent operating section for comparing an exponent of a floating point number of an operation result of a preceding multiply-add operation n with an exponent of a multiplication result of a subsequent multiply-add operation (n&plus;1), and calculating an alignment shift count of the multiply-add operation (n&plus;1) by the comparison result; and a mantissa operating section for aligning one mantissa of mantissas of two operands according to the alignment shift count inputted from the exponent operating section, calculating a sum of an aligned mantissa of the operand and the mantissa of the other operand, and normalizing a calculated addition result of the mantissas as needed, thereby calculating a mantissa of the multiply-add operation (n&plus;1). The alignment shift count is obtained by starting calculation of an alignment shift count of the subsequent multiply-add operation (n&plus;1) before normalization of the preceding multiply-add operation n is finished.

Multiply-add operating device for floating point number

A data processor has a general purpose register for storing arithmetic data and arithmetic results; an arithmetic device for MAC for performing a predetermined arithmetic operation by using the arithmetic data read from the general purpose register and outputting its arithmetic results to the general purpose register after a predetermined cycle; an arithmetic device for DIV for performing a predetermined arithmetic operation by using data read from the general purpose register and outputting its arithmetic results after a cycle longer than the predetermined cycle relative to the arithmetic device for MAC; and a temporary storing register for storing the arithmetic results outputted from the arithmetic device for DIV until the next arithmetic operation is terminated.

Arithmetic processor which latches data in a temporary register before

An instruction sequence optimization apparatus optimizes programs used in an information processing system that includes a program memory for storing programs, and a processing unit for fetching the programs from the program memory via an instruction bus. The apparatus includes an instruction sequence analyzing unit for analyzing mutual dependence relations between respective instructions constituting the program, and an instruction sequence modifying unit for modifying sequences of the instructions insofar as the mutual dependence relations analyzed by the instruction sequence analyzing unit are not influenced, to thus reduce Hamming distances between bit sequences appearing on the instruction bus when the instructions are transferred from the program memory to the processing unit.

Information processing apparatus for reducing power consumption by

Disclosed is a pipeline information processing circuit which comprises a register control unit for outputting a plurality of data held in registers at a time; an arithmetic operation unit for carrying out a collective arithmetic operation of a plurality of data; and a bypass control unit for comparing an operation result outputted from the arithmetic operation unit and a data outputted from the register control unit, selecting a data to be an object of the next arithmetic operation, and transferring the selected data to the arithmetic operation unit through a suitable bypass.

Pipeline information processing circuit for floating point operations

A floating-point division cell consisting of partial remainder data register for storing parallel-partial-remainder data or third partial remainder data, divisor data register for storing parallel-divisor data or third divisor data, low-order divisor data generator for receiving the low-order portion of the divisor data and generating low-order divisor data, low-order partial remainder calculator for obtaining low-order multi-divisor data by multiplying the low-order divisor data and a multiple of 2 together and calculating new low-order partial remainder data by subtracting or adding the low-order multi-divisor data from/to the low-order portion of the partial remainder data, high-order divisor data generator for receiving the high-order portion of the divisor data and generating high-order divisor data, and high-order partial remainder calculator for obtaining high-order multi-divisor data by multiplying the high-order divisor data and a multiple of 2 together and calculating new high-order partial remainder data by subtracting or adding the high-order multi-divisor data from/to the high-order portion of the partial remainder data.

Growing community of inventors

Kawasaki, Japan

Nobuhiro Ide