Sanyo Electric Co., Ltd.

Sanyo Semiconductor Co., Ltd.

Semiconductor Components Industries, LLC

Nobuhiko Omori

Hiroyuki Taguchi

Kouichiro Yanagi

Kazunori Chida

A video-information-processing apparatus comprising: a smoothing unit to smooth input video information of a plurality of pixels and generate smoothed video information; a subtraction unit to calculate a gradation difference between the input and smoothed video information; a mixing unit to mix the input and smoothed video information at a ratio corresponding to the difference and generate mixed video information; a determination unit to determine whether or not a peripheral pixel region, including each pixel in the input video information and pixels located around the pixel, is a low-frequency region not including a gradation change greater than or equal to a predetermined gradation change; and an output-selection unit to output the mixed video information when the determination unit determines that the peripheral pixel region is the low-frequency region and output the input video information when the determination unit determines that the peripheral pixel region is not the low frequency region.

Video information processing apparatus and recording medium having program recorded therein

A plurality of one-port split lookup tables having alternately stored therein correction data corresponding to input data is provided as a lookup table that has stored therein the correction data corresponding to the input data at predetermined intervals relevant to predetermined higher-order bits. An address generating unit generates addresses for a plurality of the corresponding split lookup tables from the input data. An interpolation arithmetic unit executes interpolation arithmetic with the use of lower-order bits of the input data for readout data read from two lookup tables.

Correction arithmetic circuit

A delay time of a reference clock CLK is changed to generate a memory control clock CLKd, a data value output from a write data generating section is written in a memory based on the memory control clock CLKd, while successively changing the delay time of the memory control clock CLKd with respect to the reference clock CLK, the data value written in the memory is read, and the delay time suitable for access to the memory is selected from the delay time of the memory control clock CLKd with respect to the reference clock CLK based on a comparison result of the data values.

Signal processing circuit for accessing a memory based on adjustable memory control clock

A horizontal contour correction circuit for correcting a horizontal contour of a video signal to output as a corrected signal, comprising: a delay circuit for outputting video signal values of a video signal at at least three different times either before or after a reference time, the video signal containing video signal values being input in a time serial manner; a plurality of selection circuits each for combining video signal values selected in advance from a group of video signal values output from the delay circuit, and selecting one video signal value from each combination of the video signal values to output; and a switch circuit for selecting one video signal value from among the video signal values output from the plurality of selection circuits. The video signal values before and after the reference time are respectively subtracted from a video signal value at the reference time, whereby horizontal contour of a video signal is corrected.

Horizontal contour correction circuit

Distortion of an image that is projected to a screen is suppressed by an image processing apparatus including a vertical reduction section for performing reduction and correction in the vertical direction with respect to image data of the projected image and a horizontal reduction section for performing reduction and correction in the horizontal direction with respect to image data on which reduction and correction were performed in the vertical reduction section.

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Gyoda, Japan

Nobuhiko Omori