Kabushiki Kaisha Toshiba

Nobuaki Yasutake

Takayuki Okamura

Jun Nishimura

Kei Sakamoto

Masaki Kondo

Takashi Izumida

Tsukasa Nakai

Takeshi Sonehara

Hikari Tajima

Mitsuhiro Omura

Takayuki Tsukamoto

Hiroshi Kanno

Yoichi Minemura

Takeshi Murata

Takamasa Okawa

Atsushi Yoshida

Satoshi Konagai

According to one embodiment, a first transistor includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a first gate insulating film, and a first gate electrode. The first semiconductor region is provided in a first semiconductor layer extending in a second direction substantially perpendicular to the surface of the semiconductor substrate from the first line. The second semiconductor region is provided above the first semiconductor region in the first semiconductor layer. The third semiconductor region is provided above the second semiconductor region in the first semiconductor layer. The first gate insulating film covers a first side face of the first semiconductor layer. The first gate electrode covers the first side face of the first semiconductor layer through the first gate insulating film. The first transistor has an asymmetrical structure with respect to a center face of the second semiconductor region in the second direction.

Semiconductor device

According to an embodiment, a semiconductor device includes two electrodes extending in a first direction, a semiconductor layer provided between the two electrodes, an insulating film disposed between the two electrodes. The two electrodes are arranged in a second direction intersecting the first direction. The semiconductor layer extends in a third direction orthogonal to the first direction and the second direction. The insulating film covers a side surface of the semiconductor layer opposite to one of the two electrodes. The semiconductor layer has a shape in a cross section perpendicular to the third direction such that a width in the first direction at a center of the cross section is narrower than a width, in the first direction, of the side surface.

According to an embodiment, a semiconductor device includes at least two control electrodes, a plurality of semiconductor layers and an insulating film. Each control electrode extends in a first direction. The semiconductor layers are provided between the control electrodes, and arranged in the first direction. Each semiconductor layer extends in a second direction orthogonal to the first direction. The insulating film covers side surfaces of the semiconductor layers, and is disposed between the control electrodes. Each semiconductor layer has a side surface that includes at least one curved surface swelling in a direction from a center of the semiconductor layer to the insulating film.

A semiconductor memory device according to an embodiment includes a memory cell array including memory cells, the memory cells each configured having a current rectifier element and a variable resistance element connected in series therein. Each of the memory cells has formed on a side surface thereof: a first insulating film provided on a side surface of the current rectifier element and the variable resistance element and having a composition ratio of a non-silicon element to silicon which is a first value; a silicon oxide film provided on a side surface of the first insulating film; and a second insulating film provided on a side surface of the silicon oxide film and having a composition ratio of a non-silicon element to silicon which is a second value. The first value is smaller than the second value.

Semiconductor memory device

An integrated circuit device according to an embodiment includes an electrode extending in a first direction, two semiconductor members spaced from each other in the first direction and extending in a second direction crossing the first direction, an insulating film placed between each of the two semiconductor members and the electrode and made of a first insulating material, and a first dielectric member placed between the two semiconductor members and made of a second insulating material having a higher permittivity than the first insulating material.

Integrated circuit device

According to one embodiment, a memory device includes: a first interconnect extending in a first direction; a plurality of second interconnects extending in a second direction intersecting with the first direction, and having lower ends positioned on the first interconnect; a plurality of third interconnects extending in a third direction intersecting with the second direction; a memory layer provided between the second interconnects and the third interconnects; and selectors respectively provided between the first interconnect and the lower ends of the plurality of second interconnects.

Memory device

A semiconductor memory device according to an embodiment includes: a memory cell array including a plurality of first lines, a plurality of second lines, and memory cells disposed at each of intersections of the first lines and the second lines; and a control circuit configured to apply a first voltage to a selected first line, apply a second voltage having a voltage value which is smaller than that of the first voltage to a selected second line, and apply a third voltage and a fourth voltage to a non-selected first line and a non-selected second line, respectively. The control circuit is configured to apply a fifth voltage to one of the non-selected first lines that is adjacent to the selected first line, and apply a sixth voltage to one of the non-selected second lines that is adjacent to the selected second line.

A non-volatile semiconductor memory device includes a cell array layer including a first wire, one or more memory cells stacked on the first wire, and a second wire formed on the memory cell so as to cross the first wire, wherein the memory cell includes a current rectifying element and a variable resistance element, and an atomic composition ratio of nitrogen is higher than that of oxygen in a part of a sidewall of the current rectifying element.

Non-volatile semiconductor memory device and method for manufacturing the same

According to one embodiment, a method for manufacturing a nonvolatile storage device. The device includes a plurality of first conductive layers each extending in a first direction, a plurality of second conductive layers each extending in a second direction and spaced from the first layers, and memory cells each provided between the first layers and the second layers and including a rectifying element including a semiconductor layer, and a variable resistance element stacked with the rectifying element. The method includes a film formation step, a heating step and a patterning step. The film formation step is configured to form a rectifying element material film including an amorphous semiconductor film. The heating step is configured to heat the rectifying element material film. The patterning step is configured to form the rectifying element including the semiconductor layer by patterning the rectifying element material film after the heating step.

Nonvolatile storage device

A nonvolatile semiconductor memory device according to an embodiment includes a memory cell block that includes a memory cell array, the memory cell array including: a plurality of first lines; a plurality of second lines intersecting the plurality of first lines; and a memory cell that is provided at each of intersections of the plurality of first lines and the plurality of second lines and includes a variable resistance element, the memory cell array further including a protective resistance film that is provided respectively at each of the intersections of the plurality of first lines and the plurality of second lines and that is connected in series with the memory cell and ohmically contacts the memory cell, and the protective resistance film being configured from a material having a resistivity of 1&#x2dc;100 &#x3a9;&#xb7;cm.

Nonvolatile semiconductor memory device with protective resistance film

According to one embodiment, a resistance change memory includes a first interconnect line extending in a first direction, a second interconnect line extending in a second direction intersecting with the first direction, a cell unit which is provided at the intersection of the first interconnect line and the second interconnect line and which includes a memory element and a non-ohmic element that are connected in series. The non-ohmic element has a first semiconductor layer which includes at least one diffusion buffering region and a conductive layer adjacent to the first semiconductor layer. The diffusion buffering region is different in crystal structure from a semiconductor region except for the diffusion buffering region in the first semiconductor layer.

Resistance change memory and method of manufacturing the same

A semiconductor memory device according to an embodiment includes a memory cell array including memory cells, the memory cells each configured having a current rectifier element and a variable resistance element connected in series therein. Each of the memory cells has formed on aside surface thereof: a first insulating film provided on aside surface of the current rectifier element and the variable resistance element and having a composition ratio of a non-silicon element to silicon which is a first value; a silicon oxide film provided on a side surface of the first insulating film; and a second insulating film provided on aside surface of the silicon oxide film and having a composition ratio of a non-silicon element to silicon which is a second value. The first value is smaller than the second value.

A memory cell comprises a diode layer, a variable resistance layer, a first electrode layer. The diode layer functions as a rectifier element. The variable resistance layer functions as a variable resistance element. The first electrode layer is provided between the variable resistance layer and the diode layer. The first electrode layer comprises a titanium nitride layer configured by titanium nitride. Where a first ratio is defined as a ratio of titanium atoms to nitrogen atoms in a first region in the titanium nitride layer and a second ratio is defined as a ratio of titanium atoms to nitrogen atoms in a second region which is in the titanium nitride layer and is nearer to the variable resistance layer than is the first region, the second ratio is larger than the first ratio.

A semiconductor memory device includes a cell array layer including a first wire, a memory cell stacked on the first wire, and a second wire formed on the memory cell. The memory cell includes a variable resistance element and a current control element The current control element includes a first conductivity-type semiconductor into which a first impurity is doped, an i-type semiconductor in contact with the first conductivity-type semiconductor, a second conductivity-type semiconductor into which a second impurity is doped, and an impact ionization acceleration unit being formed between the i-type semiconductor and one of the first conductivity-type semiconductor and the second conductivity-type semiconductor.

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Yokkaichi, Japan

Nobuaki Yasutake