Fuji Xerox Co., Ltd.

Nobuaki Miyakawa

Eiri Hashimoto

Hitoshi Ikeda

Tetsuro Kawata

Shinjiro Toyoda

Mitsumasa Koyanagi

Shinjiro Inabata

So Yamada

Noriji Kato

Yasunori Okano

Kenichi Kawauchi

Hirotsugu Kashimura

Norihiko Kuroishi

Yutaka Ueda

Jinshu Son

Reiji Aibara

When neuron operations are computed in parallel using a large number of arithmetic units, arithmetic units for neuron operations and arithmetic units for error signal operations need not be provided separately, and a neural network arithmetic apparatus that consumes the bus band less is provided for updating of synapse connection weights. Operation results of arithmetic units and setting information of a master node are exchanged between them through a local bus. During neuron operations, partial sums of neuron output values from the arithmetic units are accumulated by the master node to generate and output a neuron output value, and an arithmetic unit to which neuron operations of the specific neuron are assigned receives and stores the neuron output value outputted from the master node.

Neural network arithmetic apparatus and neutral network operation method

A three-dimensional semiconductor integrated circuit apparatus which permits ready electrical connection and is resistant to deformation and easy to fabricate and a manufacturing method therefor are provided. A second semiconductor substrate is stacked over a third semiconductor substrate, and a first semiconductor substrate is stacked over the second semiconductor substrate. A second integrated circuit is formed over the surface layer of the second semiconductor substrate, and the integrated circuit side of the second semiconductor substrate is bonded to the integrated circuit side of the first semiconductor substrate, resulting in the electrical connection of the first integrated circuit formed over the surface layer of the first semiconductor substrate and the second integrated circuit. In the second semiconductor substrate is formed embedded wiring of which one end is electrically connected to the second integrated circuit and the other end is exposed from the back side, and the third integrated circuit formed over the surface layer of the third semiconductor substrate and the second integrated circuit are electrically connected to the embedded wiring.

Three-dimensional semiconductor integrated circuit apparatus and manufacturing method therefor

To obtain the sufficiently precise result of floating-point accumulation even if the quantity of computation is enormous, a floating-point accumulator according to the present invention is constituted as follows: When two floating-point data are stored in any of shift registers, the two data are respectively output to BUS0 and BUS1 via one connected to the shift register of buffers. The two output data are input to an adder via BUS0 and BUS1 and output as added result data after adding the floating-point numbers. The above added result data is returned to each input of the shift registers via BUSW and a multiplexer and written into the shift register corresponding to the addition of the higher level by one of the shift register holding floating-point data before addition. The floating-point numbers are accumulated by repeating the above operation.

Floating-point accumulator

Electron repulsion integrals are classified according to atomic nucleus coordinates, etc., coefficients are generated and are stored in a data memory, multiplication with addition operation is executed according to a product sum procedure of auxiliary integrals of recursive order 1 or less, and the result is stored in the data memory. Next, density matrix element is stored in the data memory, a multiplication with addition operation procedure of an electron repulsion integral of recursive order 2 not containing any procedure of recursive order 1 or less is generated, and an instruction memory is updated. Multiplication with addition operation is executed while data is read from the data memory, and the result is stored in the data memory. At the termination of the product sum procedure, calculation of electron repulsion integral gRstu is complete and the Fock matrix element value is updated. The Fock matrix element containing electron repulsion integral when a linear combination constant to minimize the expected value of molecule energy required for molecular orbital calculation is found is thus found by performing recursive multiplication with addition operation.

Large-scale multiplication with addition operation method and system

A ring bus multiprocessor system whose processors are laid out and connected in such a manner that the system is enhanced in stability and performance, is easy to modify in scale, and is lowered in manufacturing cost. On a processor board, processors are serially connected by communication buses to form a processor group. Each processor board may have an even-numbered plurality of processor groups mounted thereon. A plurality of processor boards are laid out in parallel and are interconnected between adjacent boards by means of inter-processor communication buses. Each of the odd-numbered processor groups is connected from one board to the next up to the most downstream board where the connection is looped back to the adjacent even-numbered processor group. In turn, the even-numbered processor group is connected from one board to the next back to the most upstream board where the connection is again looped back to the adjacent odd-numbered processor group, and so on, whereby a ring bus arrangement is formed.

Ring bus multiprocessor system and processor boards for constituting the

A proximal particle list including numbers of particles located within a predetermined distance from a particular particle is generated in calculating a Coulomb force acting on a particular particle or a related potential. A van der Waals force acting on the particular particle or a related potential is thereafter calculated based on only the particles included in the proximal particle list.

Computing method and apparatus for a many-body problem

A device for calculating differences includes a difference circuit for generating difference signals .DELTA.x.sub.j =x.sub.j -x.sub.i, .DELTA.y.sub.j =y.sub.j -y.sub.i, and .DELTA.z.sub.j =z.sub.j -z.sub.i between coordinates of i having (x.sub.i, y.sub.i, z.sub.i) coordinate signals and coordinates of j having (x.sub.j, y.sub.j, z.sub.j) coordinate signals in an orthogonal coordinate system. The difference circuit includes an x-axis circuit, responsive to the x.sub.i and x.sub.j signals having a first circuit for receiving the x.sub.i coordinate signal and the x.sub.j coordinate signal and generating the .DELTA.x.sub.j ; a comparison circuit for comparing the x.sub.i and x.sub.j signals and determining whether the .DELTA.x.sub.j is less than a first set value -L.sub.x /2 corresponding to a length of a side of a virtual rectangular parallelepiped or greater than a second set value L.sub.x /2 corresponding to the length of the side of the virtual rectangular parallelepiped, L.sub.x being a value indicating the length of an elongated side in the x-axis direction of the virtual rectangular parallelepiped; an adder circuit for receiving the L.sub.x and .DELTA.x.sub.j and adding the L.sub.x to .DELTA.x.sub.j when .DELTA.x.sub.j is less than -L.sub.x /2; and a subtraction circuit for receiving the L.sub.x and .DELTA.x.sub.j and subtracting L.sub.x from .DELTA.x.sub.j when .DELTA.x.sub.j is greater than L.sub.x /2. The difference circuit includes y-axis and z-axis circuits similar to the x-axis circuit.

Coordinate difference calculating device

The high speed readout circuit has an amplifier unit and an operating point setting unit and reads data from a memory sense line at high speed. The circuit further includes a unit for setting an operating point of the amplifier unit by short-circuiting the input and output terminals of the amplifier in response to a first control signal and precharging the sense line up to the operating point, and a unit for setting the sense line at a voltage slightly deviating the operating point in response to a second control signal by making use of a Miller capacitance and sensing the variations from the preset voltage during a reading process.

High speed readout circuit

A power-on reset circuit including a constant voltage circuit element in which a voltage drop is limited to within a fixed value, a transistor to which a source voltage is applied from the constant voltage circuit element and a gate voltage is applied from a power source voltage to be monitored, a current path forming element, connected to the drain of the transistor, fed with current from a power source voltage, and an invertor an input terminal of which is connected to a node of the current path forming element and the transistor.

Power-on reset circuit

A digital filter processing device includes at least a plurality of multipliers each for multiplying data signal by coefficient data, and an adder for adding together the multiplication results derived from the multipliers. The digital filter processing device further includes coefficient registers each for storing the coefficient data as is shifted so that a first effective digit of the coefficient data lies at the left end, shift-quantity registers provided in connection with the coefficient registers, and each for storing a quantity of shift equal to the shift quantity of the coefficient data, and barrel shifters each for shifting the digits of an output data from each of the multipliers by the shift quantity stored in each of the shift-quantity registers, in the opposite direction to that of the shift in each of the coefficient registers. The digital filter processing device may further include a second shift-quantity register for storing a second quantity of shift, and a second barrel shifter for shifting the digits of the output data of the adder by the second shift quantity.

Digital filter processing device

An image-processing integrated circuit device comprises a delay circuit and adder group, a multiplication block group, and an adder group. Image data in a window are fed to the delay circuit and adder group simultaneously row by row and then added up for every symmetrical positions in the window. The respective sums of the image data thus added up for every symmetrical positions are multiplied by corresponding coefficient data in the multiplication block group. Lastly, the respective results of multiplication obtained from the multiplication block group are added up by the adder group to thereby obtain a filter output. The delay circuit and adder group, the multiplication block group, and the adder group can be integrated to form one image-processing integrated circuit device. Accordingly, the number of parts is reduced. Further, not only the image data can be fed into the delay circuit and adder group simultaneously but also the multiplication in the multiplication block group can be carried out in parallel and simultaneously by using exclusive multiplication blocks each provided for symmetrical positions in the window. Accordingly, the speed in filtering processing becomes high.

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Kanagawa, Japan

Nobuaki Miyakawa